1. Sequential Statements Multi-valued logic systems Bus example Case Statement Looping statement Assert statement Finite State machines

2. Numeric_std library IEEE; use IEEE.numeric_std.all; entity adder is end adder; architecture behave of adder is signal A, B, C, D : Signed(7 downto 0); begin C <= A + B; D <= a / B; end;

3. D- flip flop with asynchronous reset p1: process (x, b, reset) begin if (reset = '1') then a '0'); elsif (x = '1' and x'event) then a <= b; end if; end process p1;

4. Case Statement Selects one of a number of alternative sequences statements The chosen alternative is defined by the value of the expression choice must be of same type as the expression Case_statement ::= case expression is when choice(s) => sequential statements { when choices(s) => sequential statements } end case;

5. Example 2 p0 : process (LEAP, MONTH) begin case MONTH is when FEB => if LEAP then DAYS <= 29; else DAYS <= 28; end if; when APR | JUN | SEP | NOV => DAYS <= 30; when JUL to AUG => DAYS <= 31; when others => DAYS <= 31; end case; end process; type month_type is (JAN, FEB, MAR, APR, MAY, JUN, JUL, AUG, SEP, OCT, NOV, DEC);

6. Example 2 P3 : process begin Month <= JUL, JUN after 10 ns, OCT after 20 ns, FEB after 30 ns; LEAP <= false, true after 35 ns; wait; end process;

7. Loop Statement Three forms while for loop forever Loop_statement ::= [loop_label :] [while condition | for identifier in discrete_range] loop sequential_statements end loop [loop_label] ;

8. For Loop The identifier specifies the looping parameter need not be declared Can not be assigned to inside the loop is not visible outside the loop for i in 0 to 3 loop

9. Example 3 p1: process (a, b) variable no_ones : std_logic; begin no_ones := '0'; for i in 0 to 3 loop c(i) <= a(i) and b(i); if a(i) = '1' then no_ones := not no_ones; end if; end loop; parity <= no_ones; end process;

10. Next statement Used to complete the execution of one iteration on an enclosing loop Loop label defines which loop If no loop label specified then the inner most loop Next_statement ::= next [loop_label] [when condition];

11. exit statement Used to terminate the execution an enclosing loop Loop label defines which loop If no loop label specified then the inner most loop exit_statement ::= exit [loop_label] [when condition];

12. Example 4 loop1 : for i in 0 to 9 loop exit loop1 when A(i) > 20; next when A(i) > 10; sum := sum + A(i); end loop loop1;

13. Assert Statement Checks that a specified condition is true and reports an error if it is false Severity expression can be one of Note Warning Error Failure A VHDL simulator can terminate simulation based on a user defined severity level

14. Example 5 process (re, we, data) begin assert not (re = '1' and we = '1') report "reading and writing at same time" severity failure; if re = '1' then data <= latch; else data <= 'Z'; end if; if we = '1' then latch <= data; end if; end process;

15. Example 5

16. Finite State Machines Commonly used in digital design for control circuits Usually described as a state transition diagram e.g. a traffic light controller HYFY HG FG !cf !ch cf ch

17. Traffic Light Controller Highway Farmroad HL FL Cf HGreen <= HG Hyellow <= HY HRed <= FG or FY FGreen <= FG Fyellow <= FY Fred <= HG or HY

18. Entity Definition entity traffic is port (clock : in std_logic; CF : in std_logic; CH : in std_logic; HGreen : out std_logic; HYellow : out std_logic; HRed : out std_logic; FGreen : out std_logic; FYellow : out std_logic; FRed : out std_logic); end traffic;

19. Moore Machines Output logic Next state logic State ffs CS NS InputsOutputs Clock

20. Moore Machines in VHDL use a process for each of: Next state logic state flip-flops output logic Use an enmuerated type to represent all the states type STATE_TYPE is (HG, HY, FG, FY);

21. Traffic Light Controller - structure architecture RTL of traffic is type STATE_TYPE is (HG, HY, FG, FY); signal current_state, next_state : STATE_TYPE; begin comb: process(current_state, CF, CH) begin... end process; seq : process begin... end process; outputs:process(current_state) begin... end process; end;

22. Traffic Light Controller - next state comb: process(current_state, CF, CH) begin case current_state is when HG => if CF = '1' then next_state <= HY; else next_state <= HG; end if; when HY => next_state <= FG; when FG => if CH = '1' then next_state <= FY; else next_state <= FG; end if; when FY => next_state <= HG; end case; end process;

23. Traffic Light Controller - flip flops seq : process begin wait until clock'event and clock = '1'; current_state <= next_state; end process;

24. Traffic Light Controller - outputs outputs:process(current_state) begin HGreen <= '0'; HYellow <= '0'; HRed <= '0'; FGreen <= '0'; FYellow <= '0'; FRed <= '0'; case current_state is when HG => HGreen <= '1'; FRed <= '1'; when HY => HYellow <= '1'; FRed <= '1'; when FG => FGreen <= '1'; HRed <= '1'; when FY => FYellow <= '1'; HRed <= '1'; end case; end process;

25. Traffic Light Controller - timing

26. FSM Initialisation Simulator assumes default value of an object is its left most value In traffic light controller want FG as initial state seq : process (clock, reset) begin if reset = ‘1’ then current_state <= FG; elsif clock'event and clock = '1’ then current_state <= next_state; end if; end process;