1. Xilinx Academy 4/98 1 Xilinx Software Solutions Xilinx Academy November, 1998

2. Xilinx Academy 4/98 2

3. Xilinx Academy 4/98 3 Alliance Series Configurations $95 * * Promotional Pricing is Valid until Version 1.5 Ships in Q3 1998.

4. Xilinx Academy 4/98 4 Xilinx Alliance Series http://www.xilinx.com/products/alliance.htm Powerful High Density Solutions Integrated into Your EDA Environment

5. Xilinx Academy 4/98 5 Alliance Series Flows EDIF, VHDL, Verilog, SDF HDL Schematic Existing Designs Cores Standards Based  Includes Libraries and Interfaces for all 4 Tier One Alliance Partners  Enables multiple sources and multiple EDA vendors in the same flow  Design the way you are used to

6. Xilinx Academy 4/98 6 The Value of Partnerships The most comprehensive “Open System” solution  Early software support for new devices  New product development maximizing architectural and synthesis capabilities §Efficient timing constraints integration §High performance optimization engines tuned for new Xilinx devices §Direct optimization & mapping of Carry logic, complex I/O, LUTs, CE, arithmetic operator  Joint definition of next-generation design flows and technology

7. Xilinx Academy 4/98 7 Premier EDA Partnerships Leader in HDL Design Solutions for ASICs Leading software design solutions for system designs Leading CAE framework and industry standard Verilog simulator Leading FPGA PC schematic capture design solutions Over 50+ EDA Partnerships

8. Xilinx Academy 4/98 8 Higher Densities & Performance Requires Powerful Software 1995199719981999 Year XC4000E Largest Device XC4025E 0.5  m 5 Volt XC4000EX Largest Device XC4036EX 0.5  m 5 Volt 30% faster than E XC4000XL Largest Device 180,000 sys. gates 0.35  m 3.3 Volt 30% faster than EX XC4000XV Largest Device 500,000 sys. gates 0.25  m 2.5 Volt 30% Faster than XL 1996 Virtex 1M+ Systems Gates System Solution 0.25/0.18µ 2.5/1.8 Volt Density/Performance 1 Million Gates in 1998 1 Million Gates in 1998

9. Xilinx Academy 4/98 9 The Alliance Series Advantage Only Xilinx delivers these essential capabilities Powerful timing-driven technology & graphical Constraints Editor Highest performance with industries leading synthesis vendors Dramatic productivity improvements with the Core Generator Support for industries highest density FPGA XC40250XV 500K system gates Guarantee your design performance with min & max timing

10. Xilinx Academy 4/98 10 Expanding the Leadership The latest Xilinx software delivers Support for the industry’s 1 st 1M gate FPGA Designs The industries fastest timing-driven compile times 50% faster compile times Max Design performance: AKAspeed tm technology Up to 30% faster performance Higher productivity with HDL Simulators Model Technology Eval in the Box

11. Xilinx Academy 4/98 11 Performance Based Design Timing Driven Technology  Maximum Device Performance —Achieve max design performance: AKA speed tm technology —Robust timing constraints language, SMARTspecs —40% Higher Performance with the Floorplanner —Xilinx Core Generator —Industry’s Fastest Devices  Highest Area Utilization Available —> 95% Device Utilization  Flexibility —Freedom to choose the most cost effective device —Design changes with repeatable performance

12. Xilinx Academy 4/98 12 Achieve Maximum Performance with AKAspeed tm Technology Optimized for Today’s Higher Performance Higher Density Designs Minimum delays Voltage and temperature prorating Graphical constraints editor Graphical Floorplanner Integration with CORE Generator Timing-driven implementation K-paths Advanced timing analysis algorithms Robust timing language Incremental Designing Cores New Algorithms Features Enhancements to v1.4

13. Xilinx Academy 4/98 13 Flexibility Provides a Productivity Edge  Flexibility —Freedom to choose the most cost effective device —Design changes with repeatable performance  Easy to track design change with revision control  Instant software access with registration-based security  Extensive Platform/OS Support —Win95, WinNT 4.0, NEC PC98 —Chinese, Korean & Japanese Windows —Solaris 2.5 & 2.6, HP-UX 10.2, IBM RS6000 AIX 4.1.5 —CDE

14. Xilinx Academy 4/98 14  Guides user to the best constraint methodology  Eliminates need for user knowledge of syntax  Reduces need for user knowledge of design nets & components Constraint Entry Made Easier

15. Xilinx Academy 4/98 15 Floorplanner  Specify physical placement to reduce routing delays & increase performance up to 40%  Area constraints for modules provide  faster runtimes  higher performance  design changes made easier

16. Xilinx Academy 4/98 16 HDL Verification We will take you to the leaders  Why simulate? nReduce time-to-market 25% nErrors early in the design cycle (RTL) are inexpensive to fix nBottom up and team design for large designs require each module to be verified nIt takes twice as long to isolate a bug in hardware than in simulation  Xilinx will take you to the leaders nVisit our HDL Verification Website for our premier partners, articles & design guides http://www.xilinx.com/products/alliance/verifi.htm

17. Xilinx Academy 4/98 17 Bus Interface Memory Interface DMA Module Custom Design App Specific Module Processor Cores are essential to High Density Designs  General purpose delivery vehicle for IP  Predictable & repeatable Independent of device size Constant performance as more cores are added Advance specification  Compatible with HDL Design Flows High Performance Reduce Design Time

18. Xilinx Academy 4/98 18 1999 2000 Features and Enhancements Alliance 2.1 New Device Families Reduced Runtimes Ease of Use Enhanced Synthesis QOR & Flows Modular & Team Design Guide for Synthesis Enhanced Core Generator Integration Improved HDL Verification Flows System Verification Support HDL + Cores + ASIC tools 1M Gates Alliance 2.1 New Device Families Reduced Runtimes Ease of Use Enhanced Synthesis QOR & Flows Modular & Team Design Guide for Synthesis Enhanced Core Generator Integration Improved HDL Verification Flows System Verification Support HDL + Cores + ASIC tools 1M Gates Alliance Future New Device Families Reduced Runtimes Ease of Use Enhanced Synthesis QOR Core Generator Enhancements Modular & Team Design Enhancements Guide for Synthesis HDL + Cores + ASIC tools 2M Gates Alliance Future New Device Families Reduced Runtimes Ease of Use Enhanced Synthesis QOR Core Generator Enhancements Modular & Team Design Enhancements Guide for Synthesis HDL + Cores + ASIC tools 2M Gates Alliance Series Leading Xilinx into Year 2000

19. Xilinx Academy 4/98 19

20. Xilinx Academy 4/98 20 Foundation Series Configurations $95 * $495 * * Promotional Pricing is Valid until Version 1.5 Ships in Q3 1998.

21. Xilinx Academy 4/98 21 21 Xilinx Ready to Use Design Solutions

22. Xilinx Academy 4/98 22 22 Ready-To-Use Design Solutions  Everything you need in one box  Highest FPGA/CPLD performance & density  Superior HDL design solution  Unequaled Value! Graphical Design Flow  Walks you through entire design process  Integrates all tools in one environment Schematic Capture and HDL Design Entry Simulation Synthesis Optimization Implementation

23. Xilinx Academy 4/98 23 Xilinx Foundation Series  Instant Productivity  Superior HDL Solution  Push-Button, High Performance Design  Supports All Xilinx Devices

24. Xilinx Academy 4/98 24 Instant Productivity  Intuitive GUIs  Powerful Design Wizards  Mixed-Level Design Environment  Push-Button Flows  Best in Class EDA tools in a Unified Design EnvironmentFOUNDATION Series Software

25. Xilinx Academy 4/98 25 25 FPGA Express Synthesis Window Superior HDL Design Solution Graphical Constraint Entry Graphical State Editor Synopsys FPGA Express Embedded Mixed-Language Entry and Synthesis Graphical HDL entry HDL Simulation* Time Tracker TM * Free evaluation software delivered in box. Permanent licenses sold separately by partnersFOUNDATION Series Software State Diagram Entry

26. Xilinx Academy 4/98 26 26 High-Performance Design, Push- Button Design Flows  Advanced Synthesis and Optimization from Synopsys  New A.K.A. speed Technology —Graphical Constraint Entry and Static Timing Analysis  Integrated CORE-Generator  Supporting the industry’s leading Programmable Logic DevicesFOUNDATION Series Software

27. Xilinx Academy 4/98 27 Complete High Volume Solution  Foundation Base Express —Ready-to-Use Software Solution —Synopsys Synthesis, Push-Button Flows, and Low Price  Spartan / XL FPGAs —No Compromises Architecture —Performance, RAM, Cores, and Low Price  XC9500 / XL CPLDs —Most Flexible JTAG ISP Devices —Fastest Speed, Best Pin-Locking, and Low PriceFOUNDATION Series Software

28. Xilinx Academy 4/98 28 Productivity Edge Design Wizards Graphical VHDL and Verilog Entry Synopsys Synthesis Performance Driven Design (A.K.A. Speed technology) Complete High Volume Solution Best Programmable Logic Performance/Density/Power VHDL / Verilog Simulation (Free Evaluation software in the box) Mixed-Level, Mixed-Language Design Best Timing Driven Compile Time 4 Only Xilinx Delivers These Essential Capabilities 4 4 4 4 4 4 4 4FOUNDATION Series Software

29. Xilinx Academy 4/98 29 Foundation Series Product Roadmap Now Shipping! Foundation Ease-of-Use enhancements Internet Access New HDL templates Advanced Performance Features Express 2.1.3 synthesis New Device Support: Virtex (production ) Japanese Localization Nov 1998 F1.5 F1.5i / F1.5J (minor release) Foundation Ease-of-Use enhancements Improved Push-Button Automation Improved Error Navigation Improved Version Control CPLD Floorplanner Advanced Performance Features Improved Simulator Capacity / Performance Express 3.1 / Schematic Viewer New Device Support: Spartan II, XC9500XV Mid 1999 F2.1 Foundation Ease-of-Use enhancements Unified Project Mgmt. Express Embedded Plug-and-Play HDL Simulation solutions Advanced Performance Features (A.K.A. Speed) Constraints Editor Floorplanner Min Delay, Temp/Volt Pro-rating New Device Support: Virtex (Beta), 9KXL, 4KXLA, SpartanXL device supportFOUNDATION Series Software

30. Xilinx Academy 4/98 30 Summary  Xilinx Software Solutions — Fits customer’s methodology — Best performance and utilization — Rich implementation tool set — Repeatable and adaptable designs via – Industry’s best pin-locking – Richest timing constraint language 199719981999 2000 Gates: 85K Freq.: 65MHz+ Gates: 250K Freq.: 100 MHz+ Gates: 500K Freq.: 200 MHz+

31. Xilinx Academy 4/98 31 Sell BAS & BSX Now! FND-STD $3995 Schematic HDL Low-Density (<10K gates) All Densities FND-BAS $495 $95! X FND-BSX $1495 X $495! Software Product Configurations FND-EXP $4995 ALI-BAS-PC $495 X $95! $4,995 = 37% Price Reduction $4,995 = 37% Price Reduction All Promotional Pricing has been Extended thru mid-98

32. Xilinx Academy 4/98 32 Future Direction Responding to the Changing Landscape Schematic Single designer Timing Driven PAR Synthesis Single designer HDL Back Annotatio n Synthesis and Cores Small team Tighter ties with synthesis vendors Cores, HDL, Design reuse, Behavioral compiler Larger design teams Module Compile Module Guide TIMELINE Evolution of FPGA Tools Evolution of FPGA Design

33. Xilinx Academy 4/98 33 Future Software Flow Design Entry is Evolving Design Reuse Cores Synthesized HDL Behavior Compile Simulation or Formal Verification Bitstream  Large, predefined functions  Individual modules  Team based environment Same flow as today

34. Xilinx Academy 4/98 34 Future Direction Modular Design is the Key  Seamless Integration between modules  Modular Timespecs  Module Based Incremental Compile  BENEFIT = Reduced compile times  BENEFIT = Higher performance designs Vendor A Core Module Vendor B Core Team1 Design Team3 Design Team2 Design Reuse

35. Xilinx Academy 4/98 35 1.5 is HOT 1.5 Delivers What Customers are Requesting  Runtime Improvements  Constraints Editor  Floorplanner  Automatic Pin Locking  Faster Timing Analysis (Kpaths algorithm)  Automatic Clock Skew Handling  New Reporting of Minimum Delays  Improvements to Constraint Language  Still More Improvements to Reports  New ‘xilinx’ Command Launches Tools on WS’s

36. Xilinx Academy 4/98 36 L1 L3 L2 (1.4 default) L4 L5 Clock Speed Runtime 1.3 Default L=PAR Effort Level New Defaults Speed Runtime