1. SOC Design Lecture 2 Lecture Goal

2. YOUPYO HONG, DGU Our Final Goal in This Course is To Design AHB-compatible SRAM controller.

3. YOUPYO HONG, DGU Steps to Accomplish the Goal To understand SRAM operation To obtain (or design) SRAM RTL model To test out the SRAM RTL model To understand AHB

4. YOUPYO HONG, DGU SRAM We are talking about On-chip SRAM We are talking about Synchronous SRAM We will use Behavioral Model of SRAM

5. YOUPYO HONG, DGU HW #1 Obtain or Design a synchronous SRAM using Verilog. Width 32bit. Depth 128 (or more). Draw a timing diagram for write and read operation. Due in one week.