1. Computer Architecture Lecture 5 Sequential Circuits Ralph Grishman September 2015 NYU

2. Finite-state machine0 A sequential circuit is a finite-state machine 9/21/15Computer Architecture lecture 52

3. General form The general sequential circuit has separate comb. circuits for next-state and output: 9/21/15Computer Architecture lecture 53

4. A simpler version We will consider a simpler design where the output is part of the current state: 9/21/15Computer Architecture lecture 54 current state next state output input

5. Finite State Transition Network The next-state function can be represented by a graph: a finite state transition network network has nodes and arcs each node represents a state of the circuit each arc represents a possible transition between states – arc is labeled by condition under which transition is made 9/21/15Computer Architecture lecture 55

6. Up Counter no input 9/21/15Computer Architecture lecture 56 11 10 00 01

7. Up-down Counter input: 0  up 1  down 9/21/15Computer Architecture lecture 57 11 10 00 01 0 0 0 0 1 1 1 1

8. Transition Table A transition table has – input columns corresponding to current state – input columns corresponding to circuit input – output columns representing next state 9/21/15Computer Architecture lecture 58

9. Up Counter input (current state)output (next state) 0001 0110 1011 1100 9/21/15Computer Architecture lecture 59

10. Up-down counter inputcurrent statenext state 00001 00110 01011 01100 10011 10100 11001 11110 9/21/15Computer Architecture lecture 510

11. How to design a sequential circuit 1. draw the transition network 2. build the transition table (i.e., the truth table of the ‘next state’ circuit) 3. convert transition table to a formula and then to a circuit 4. add register and clock connections 9/21/15Computer Architecture lecture 511

12. Up Counter no input 9/21/15Computer Architecture lecture 512 11 10 00 01

13. Up Counter input (current state)output (next state) 0001 0110 1011 1100 9/21/15Computer Architecture lecture 513

14. Up Counter current statenext state 0001 0110 1011 1100 9/21/15Computer Architecture lecture 514 next 0 = current 0 next 1 = current 0 current 1 ⊕

15. Up-Counter: complete 9/21/15Computer Architecture lecture 515 out C

16. Up-down Counter input: 0  up 1  down 9/21/15Computer Architecture lecture 516 11 10 00 01 0 0 0 0 1 1 1 1

17. Up-down counter inputcurrent statenext state 00001 00110 01011 01100 10011 10100 11001 11110 9/21/15Computer Architecture lecture 517

18. Up-down counter inputcurrent statenext state 00001 00110 01011 01100 10011 10100 11001 11110 9/21/15Computer Architecture lecture 518 next 0 = ? next 1 = ?

19. Traffic light Example from text (slightly simplified) Two states: – EW lite = show green EW, red NS – NS lite = show red EW, green NS Two inputs: – EW car = car entering from E or W – NS car = car entering from N or S Strategy: – flip traffic light if a car is waiting in the direction currently marked as red 9/21/15Computer Architecture lecture 519

20. Traffic light: transition network 9/21/15Computer Architecture lecture 520 NSlite EWlite

21. Traffic light: transition network 9/21/15Computer Architecture lecture 521

22. Traffic light: transition table current stateNS carEW carnext state NS lite00 01 10 11 EW lite00 01 10 11 9/21/15Computer Architecture lecture 522

23. Traffic light: transition table current stateNS carEW carnext state NS lite00 01EWlite NS lite10 11EWlite 00 01 10NSlite EW lite11NSlite 9/21/15Computer Architecture lecture 523

24. Traffic light: transition table current stateNS carEW carnext state NS lite00 01EWlite NS lite10 11EWlite 00 01 10NSlite EW lite11NSlite 9/21/15Computer Architecture lecture 524 let NSlite be state 0 and EW lite be state 1 next state = ?

25. Traffic light: transition table current stateNS carEW carnext state NS lite00 01EWlite NS lite10 11EWlite 00 01 10NSlite EW lite11NSlite 9/21/15Computer Architecture lecture 525 next state = currentState  EWcar + currentState  NScar

26. Larger memories Static Random-Access Memories (SRAMs) are essentially large register arrays Used for caches Two-dimensional layout reduces size of multiplexers and decoders 9/21/15Computer Architecture lecture 526

27. 4 X 2 SRAM 9/21/15Computer Architecture lecture 527

28. Dynamic RAMs Dynamic RAMs (DRAMs) use a single transistor + capacitor for each bit – two-dimensional layout – density is considerably higher than SRAMs, but they are slower have to be regularly refreshed (read and rewritten) – used for main memory 9/21/15Computer Architecture lecture 528

29. DRAM 9/21/15Computer Architecture lecture 529