1. George Mason University ECE 448 – FPGA and ASIC Design with VHDL FPGA Design Flow based on Aldec Active-HDL FPGA Board

2. George Mason University ECE 448 – FPGA and ASIC Design with VHDL FPGA Design Flow

3. 3ECE 448 – FPGA and ASIC Design with VHDL Design flow (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Specification (Lab Experiments) VHDL description (Your Source Files) Functional simulation Post-synthesis simulation Synthesis

4. 4ECE 448 – FPGA and ASIC Design with VHDL Design flow (2) Implementation Configuration Timing simulation On chip testing

5. 5 Tools used in FPGA Design Flow Synplicity Synplify Pro Synplicity Synplify Pro Design Synthesis Implementation Xilinx ISE VHDL code Netlist Bitstream Xilinx XST Functionally verified VHDL code

6. George Mason University ECE 448 – FPGA and ASIC Design with VHDL Synthesis

7. 7ECE 448 – FPGA and ASIC Design with VHDL Synthesis Tools … and others Synplify Pro Xilinx XST

8. 8ECE 448 – FPGA and ASIC Design with VHDL architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW; VHDL description Circuit netlist Logic Synthesis

9. 9ECE 448 – FPGA and ASIC Design with VHDL Circuit netlist (RTL view)

10. 10ECE 448 – FPGA and ASIC Design with VHDL Mapping LUT2 LUT3 LUT4 LUT5 LUT1 FF1 FF2 LUT0

11. RTL view in Synplify Pro increment er comparator General logic structures can be recognized in RTL view MUX

12. Crossprobing between RTL view and code Each port, net or block can be chosen by mouse click from the browser or directly from the RTL View By double-clicking on the element its source code can be seen: Reverse crossprobing is also possible: if section of code is marked, appropriate element of RTL View is marked too:

13. Technology View in Synplify Pro Technology view is a mapped RTL view. It can be seen by pressing button or by double-click on “.srm” file As in case of “RTL View”, buttons can be used here Two additional buttons are enabled: - show critical path - open timing analyst - open timing analyst Technology view is presented using device primitives Ports, nets and blocks browser Pay attention: technology view is usually large and presented on number of sheets

14. Viewing critical path Critical path can be viewed by pressing on Delay values are written near each component of the path

15. Timing Analyst Timing analyst opened by pressing on Timing analyst gives a possibility to analyze different paths in the design Timing analyst can be opened only from Technology View

16. George Mason University ECE 448 – FPGA and ASIC Design with VHDL Implementation

17. 17ECE 448 – FPGA and ASIC Design with VHDL Implementation After synthesis the entire implementation process is performed by FPGA vendor tools

18. 18ECE 448 – FPGA and ASIC Design with VHDL

19. 19ECE 448 – FPGA and ASIC Design with VHDL Translation UCF NGD EDIF NCF Native Generic Database file Constraint Editor or Text Editor User Constraint File Native Constraint File Electronic Design Interchange Format Circuit netlistTiming Constraints Synthesis

20. 20ECE 448 – FPGA and ASIC Design with VHDL Pin Assignment LAB2 CLOCK CONTROL(0) CONTROL(2) CONTROL(1) RESET SEGMENTS(0) SEGMENTS(1) SEGMENTS(2) SEGMENTS(3) SEGMENTS(4) SEGMENTS(5) SEGMENTS(6) H3 K2 G5 K3 H1 K4 G4 H5 H6 H2 P10 B10 FPGA

21. 21ECE 448 – FPGA and ASIC Design with VHDL

22. 22ECE 448 – FPGA and ASIC Design with VHDL Mapping LUT2 LUT3 LUT4 LUT5 LUT1 FF1 FF2 LUT0

23. 23ECE 448 – FPGA and ASIC Design with VHDL Placing CLB SLICES FPGA

24. 24ECE 448 – FPGA and ASIC Design with VHDL Routing Programmable Connections FPGA

25. 25ECE 448 – FPGA and ASIC Design with VHDL Configuration Once a design is implemented, you must create a file that the FPGA can understand This file is called a bit stream: a BIT file (.bit extension) The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information

26. Two main stages of the FPGA Design Flow Synthesis Technologyindependent Technologydependent Implementation RTL Synthesis Map Place & Route Place & Route Configure - Code analysis - Derivation of main logic constructions - Technology independent optimization - Creation of “RTL View” - Mapping of extracted logic structures to device primitives - Technology dependent optimization - Application of “synthesis constraints” -Netlist generation - Creation of “Technology View” - Placement of generated netlist onto the device -Choosing best interconnect structure for the placed design -Application of “physical constraints” - Bitstream generation - Burning device

27. 27ECE 448 – FPGA and ASIC Design with VHDL Static Timing Analysis

28. 28ECE 448 – FPGA and ASIC Design with VHDL Static Timing Analyzer Performs static analysis of the circuit performance Reports critical paths with all sources of delays Determines maximum clock frequency

29. 29ECE 448 – FPGA and ASIC Design with VHDL Static Timing Analysis Critical Path – The Longest Path From Outputs of Registers to Inputs of Registers DQ in clk DQ out t P logic t Critical = t P FF + t P logic + t S FF

30. 30ECE 448 – FPGA and ASIC Design with VHDL Static Timing Analysis Min. Clock Period = Length of The Critical Path Max. Clock Frequency = 1 / Min. Clock Period

31. 31ECE 448 – FPGA and ASIC Design with VHDL Timing Characteristics of Combinational Circuits Combinational Circuits Are Characterized by Propagation Delays through logic components (gates, LUTs) through interconnects (routing delays) t p LUT t p routing LUT Total propagation delay through combinational logic

32. 32ECE 448 – FPGA and ASIC Design with VHDL Timing Characteristics of Combinational Circuits (2) Total Propagation Delay of Logic Depends on the Number of Logic Levels and Delays of Logic Components Number of logic levels is the number of logic components (gates, LUTs) the signal propagates through Routing Delays Depend on: Length of interconnects Fanout

33. 33ECE 448 – FPGA and ASIC Design with VHDL Timing Characteristics of Combinational Circuits (3) Fanout – Number of Inputs Connected to One Output Each inputs has its capacitance Fast switching of outputs with high fanout requires higher currents and strong drivers LUT

34. 34ECE 448 – FPGA and ASIC Design with VHDL Timing Characteristics of Combinational Circuits (4) In Current FPGAs Routing Delays typically account for 45% to 65% of the total path delays

35. 35ECE 448 – FPGA and ASIC Design with VHDL Timing simulation after implementation

36. 36ECE 448 – FPGA and ASIC Design with VHDL Timing vs. functional simulation Simulation before synthesis is used to verify circuit functionality and may differ from the one after synthesis and implementation Implementation tool generates SDF (Standard Delay Format) as a standard delay file and the netlist for synthesized VHDL code with delays. Generated netlist contains many component instantiation statements with library references

37. 37ECE 448 – FPGA and ASIC Design with VHDL SDF file ( DELAYFILE ( CELL( CELLTYPE “XOR”) ( INSTANCE U34.Z_VTX) ( DELAY( INCREMENT ( DEVICE 01 0.385090:0.385090:0.385090 (0.385090:0.385090:0.385090)(0.235177: 0.235177: 0.235177) ) ) ) ) A part of the SDF file is shown below. It indicates XOR gate delays (low to high, high to low) of minimum, typical and worst case timing

38. 38ECE 448 – FPGA and ASIC Design with VHDL Netlist from the synthesis tool library IEEE; library TC200G; use IEEE.std_logic_1164.all; use TC200G.components.all; entity CONSYN is port( RSTn, CLK, D0, D1, D2, D3, D4, D5, D6, D7 : in std_logic; FF_OUT, COMB_OUT, FF_COMB_OUT : out std_logic); end CONSYN; architecture structural of CONSYN is signal XOR8, FF, n70, n71, n72, n73, n74, n75, n76, n67, n68, n69 : std_logic; begin FF_OUT <= FF; COMB_OUT <= XOR8; FF_reg : FD2 port map( Q => FF, QN => n75, D => XOR8, CP => CLK, CD => RSTn) ; U30 : MUX21L port map( Z => n71, A => n67, B => n68, S => n69); U31 : EN port map( Z => n67, A => D1, B => D0); U32 : IV port map( Z => n68, A => n67); U33 : EOP port map( Z => n69, A => D6, B => D7); U34 : EO3 port map( Z => n70, A => D3, B => D2, C => D4); U35 : EO port map( Z => n72, A => D5, B => n70); U36 : EOP port map( Z => XOR8, A => n72, B => n71); U37 : FA1A port map( S => n73, CO => n76, CI => D3, A => D2, B => FF); U38 : EO3 port map( Z => n74, A => n68, B => n73, C => D4); U39 : EOP port map( Z => FF_COMB_OUT, A => D5, B => n74); end structural;

39. George Mason University ECE 448 – FPGA and ASIC Design with VHDL Celoxica RC10 FPGA Board

40. 40ECE 448 – FPGA and ASIC Design with VHDL

41. 41ECE 448 – FPGA and ASIC Design with VHDL

42. 42ECE 448 – FPGA and ASIC Design with VHDL

43. 43ECE 448 – FPGA and ASIC Design with VHDL

44. 44ECE 448 – FPGA and ASIC Design with VHDL

45. 45ECE 448 – FPGA and ASIC Design with VHDL

46. Joystick needs to be debounced (you can use circuit from experiment 2) input output DD clock cycles

47. 47ECE 448 – FPGA and ASIC Design with VHDL Piezo Buzzer Outputted signals should be 50% duty square waves, meaning the signal is high and low for equal amounts of time.

48. 48 Demo

49. 49 Exp.2: Part 2 Programmable (joystick) timer (counter + clock divider) with alarm (buzzer).

50. 50ECE 448 – FPGA and ASIC Design with VHDL Questions?

51. 51ECE 448 – FPGA and ASIC Design with VHDL Hands-on Session Enough Talking Let’s Get To It !!Brace Yourselves!!