1. 1 19 th January 2009 M. Mager - L. Musa Charge Readout Chip Development & System Level Considerations

2. 2 19 th January 2009 M. Mager - L. Musa anode wire pad plane drift region 88  s L1: 5  s 200 Hz PASA ADC Digital Circuit RAM 8 CHIPS x 16 CH / CHIP 8 CHIPS x 16 CH / CHIP CUSTOM IC (CMOS 0.35  m) CUSTOM IC (CMOS 0.25  m ) DETECTOR FEC (Front End Card) - 128 CHANNELS (CLOSE TO THE READOUT PLANE) FEC (Front End Card) - 128 CHANNELS (CLOSE TO THE READOUT PLANE) 570132 PADS 1 MIP = 4.8 fC S/N = 30 : 1 DYNAMIC = 30 MIP CSA SEMI-GAUSS. SHAPER GAIN = 12 mV / fC FWHM = 190 ns 10 BIT < 10 MHz BASELINE CORR. TAIL CANCELL. ZERO SUPPR. MULTI-EVENT MEMORY L2: < 100  s 200 Hz DDL (3200 CH / DDL) Power consumption: < 40 mW / channel Power consumption: < 40 mW / channel gating grid ALTRO Front End Electronics Architecture Alice TPC FEE – MWPC Readout

3. 3 19 th January 2009 M. Mager - L. Musa 19 cm 17 cm Top Side PASA CHIP ALTRO CHIP Power Regulation Board Controller (FPGA) Alice TPC FEE – MWPC Readout 128-channel Front End Card

4. 4 19 th January 2009 M. Mager - L. Musa ALICE TPC Front End Card: Layout, Cooling and Mounting COOLING PLATES (COPPER) WATER COOLING PIPE INNER READOUT CHAMBER Shaping Amplifiers ALTROs current monitoring & supervision voltage regulators power connector control bus connector readout bus connector GTL transceivers (back side) 155 mm 190 mm

5. 5 19 th January 2009 M. Mager - L. Musa PAD SIDE 5504 pad (4x7.5 mm 2 ) CONNECTOR SIDE Pad plane close-up view ≈ 570 000 pads (36 sectors) ALICE TPC - Readout Chambers

6. 6 19 th January 2009 M. Mager - L. Musa Installation of ALICE Front End Electronics (Feb-May ’06)

7. 7 19 th January 2009 M. Mager - L. Musa ALICE TPC in June ‘06

8. 8 19 th January 2009 M. Mager - L. Musa A general purpose charge readout chip for MPGDs number of channels: 32 or 64 programmable charge amplifier sensitive to a charge in the range: ~10 2 - ~10 6 electrons Peaking time: 30ns – 120ns high-speed high-resolution A/D converter sampling rate:40MHz programmable digital filter for noise reduction and signal interpolation; a signal processor for the extraction and compression of the signal information (charge and time of occurrence). Two readout modes: external trigger or self-triggered Trigger can have any position wrt the acquisition window Standby mode Charge readout chip for MPGD

9. 9 19 th January 2009 M. Mager - L. Musa Charge Readout Chip Block Diagram 32 / 64 Channel Charge Amplifier Anti- Aliasing Filter ADC Signal Processor Data Compression Multi-Acq Memory Charge Amplifier Anti- Aliasing Filter ADC Signal Processor Data Compression Multi-Acq Memory Charge Amplifier Anti- Aliasing Filter ADC Signal Processor Data Compression Multi-Acq Memory INTERFACEINTERFACE

10. 10 19 th January 2009 M. Mager - L. Musa Charge Readout Chip – Amplifier and ADC  16-channel 4th order CSA  programmable polarity  programmable gain: 12-27 mV/fC  Programmable peaking time: 30-120ns  Process: IBM CMOS 0.13  m  area: 3 mm 2  1.5 V single supply, power: <8mW/channel  MPR samples (1000): May 07 16-channel Shaping amplifier prototype Gerd Trampitsch Layout of 12-channel PASA prototype Layout of 2-channel ADC prototype  10-bit ADC, 40MHz sampling frequency  Pipelined differential architecture  Process: IBM CMOS 0.13  m  area: 0.7 mm 2  1.5 V single supply  Power/channel: 33mW @ 40MHz, 18mW @ 20MHz  MPR samples (40): Jan 09 2-channel ADC prototype Hugo Franca Santos

11. 11 19 th January 2009 M. Mager - L. Musa Charge Readout Chip – Digital Data Processor Global Architecture RB: ring buffer, DSC: digital signal conditioner, PF: pulse finder ZS: zero suppression, MEB: multi event buffer (3D) pulse/peak finderChip interconnection scheme Main Features  Programmable architecture o trigger related acquisition o trigger-less acquisition o free pos. of acq. window  Flexible use of memory  Full digital signal conditioning  3D zero suppression  Integrated readout network

12. 12 19 th January 2009 M. Mager - L. Musa Considerations on readout plane IC Area (die size) 1-2 mm 2 /channel Shaping amplifier 0.2 mm 2 ADC0.7 mm 2 (prototype  room for improvement) Digital processor0.6 mm 2 (estimate) in the following we consider the case of 1.5mm 2 / channel 64 ch / chip  ~ 100 mm 2 Area of the chip on the PCB: 14 x 14 mm 2 / chip  ~ 3 mm 2 / pad PCB dimensions < 40 x 40 cm 2  20000 pads (8mm 2 /pad), ~300 FE chips / board

13. 13 19 th January 2009 M. Mager - L. Musa PCB topology and layer stack-up Pad layer Pad signals routing det gnd Digital signals I gnd vdd Digital signals II gnd 8-layer PCB Considerations on readout plane amplifiers ADCs Digital Processing Chip floorplan Flip-chip mounted PCB amplifiers ADCs Digital Processing Analogue PWR planes Digital PWR planes

14. 14 19 th January 2009 M. Mager - L. Musa Considerations on power consumption & cooling Power consumption (for 30ns peaking time, 40Mhz sampling, 3mm 2 pad) amplifier 8 mW / channel ADC30 mW / channel Digital Proc 4 mW / channel Power regulation and links 10 mW / channel duty cycle:1% average power / channel ~ 0.5 mW / channel average power / m 2 167 W PCB cooling plate cooling pipes