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15-348 Embedded Systems Lecture 5 January 25 th, 2016.

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Presentation on theme: "15-348 Embedded Systems Lecture 5 January 25 th, 2016."— Presentation transcript:

1 15-348 Embedded Systems Lecture 5 January 25 th, 2016

2 Road Map  What have we done  Gotten familiar with embedded hardware  Bit manipulation in C  Input and Output using I/O ports  What we plan on doing  Programming in Assembly Language  What you should do  Read pages 60-79 from the textbook

3 Registers in 9S12  CCR – Condition Code Register  S – Stop Bit: Used to enable stop mode for power saving  X – Interrupt Mask:  I – Interrupt Mask:  C – Carry Flag: Set when carry out from D7  V – Overflow Flag: Set for signed overflow  Z – Zero Flag: Set when result is zero  N – Negative Flag: Set when result is negative  H – Half-byte carry Flag: Set when carry from D3 to D4 SXHIN Z V C 8-bit condition code

4 Registers in 9S12  Two 8-bit accumulators  Two 16-bit index registers (X and Y)  16-bit stack pointer SP  16-bit program counter PC Register ARegister B Register D

5 Memory Structure of MC9S12C128 0x0000 0x0400 0x1000 0x4000 0xFF00 0xFFFF 0x0000 – 0x03FF 1K Register Space 0x0400 – 0x1000 ~4K RAM 0x4000 – 0xFF00 ~128K ROM (EEPROM) 0xFF00 – 0xFFFF Vector Space

6 Using the RAM Global Variables RAM 4K Bytes Available Memory Stack grows down Stack Stack Pointer

7 Using ROM  Fixed Constants  Strings  Calibration values  ID numbers  Finite State Machines  Device Address Fixed Constants Machine Code Vector Table PC

8 What is assembly language  Machine code in human readable format  Human readable is of course relatively speaking  E.g. DDRT equ $0x0240 ldaa #$0F860F staa DDRT7A0240 860F7A0240 Assembly Language Equivalent Machine code Real Machine code

9 Assembly Format  Each field separated by whitespace [Label] Instruction [Operands] [Comments] PORTAequ $0000 Inpldaa PORTA ; read input Labelclra deca ; decrement a bne Label  The operand field depends on the operation

10 Assembly Instructions  Two main kinds of instructions  Operations  Assembler Directives DDRT equ $0x0240  Assembler Directive ldaa #$0F  Load Operation staa DDRT  Store Operation

11 Load instructions  ldaaload accumulator a  ldabload accumulator b  lddload register d  ldxload index register x  ldyload index register y  ldsload Stack Pointer 16 bit move

12 Addressing modes (load what?)  ldaa#wLoad the value w in a  ldaaULoad the value at address U  All load instructions set the N and the Z bit in CCR

13 Store instructions  staaU  stab  std  stx  sty  sts  All store instructions set the N and the Z bit in CCR

14 Example C code: DDRB = 0x45; PORTB = 0x23 Assembly Code: LDAA #$45 STAA $03 ; DDRB is address 3 LDAB #$23 STAB $01 ; PORTB is address 1

15 More addressing modes  Indexed staa -4,YReg a  Address Y- 4 staa$40,YReg a  [Y+$40]  Auto inc/dec Indexed staa 1, Y+ Reg a  [Y] and Y = Y+1 staa 4, Y+ Reg a  [Y] and Y = Y+4 staa 4, +Y Reg a  [Y + 4] and Y = Y+4 [Y-4]

16 More addressing modes  Accumulator Offset Indexed ldab #4 ldy #2345 staa B,Y ;store contents of a at 2349

17 Arithmetic Operations  8-bit Add adda#w ; RegA=RegA + w addaU ; RegA = RegA +[U] addb#w ; RegB=RegB + w addbU ; RegB = RegB +[U]  Add instructions sets the N, Z, V, and C bits in CCR

18 16-bit add addd#W; RegD = RegD + W addd#U; RegD = RegD + [U] Example: ldd$1234 addd#1000 std$1238

19 Example C code: byte a = 23; byte b = 12; PORTA = a + b Assembly Code: LDAA #23 ADDA #12 STAA $00; PORTA is address 0

20 Subtract suba#w;RegA = RegA – w cmpa#w; RegA – w tsta; RegA – 0 cpd#W; RegD – W subdU; RegD – [U] deca; RegA = RegA -1 incb; RegB = RegB +1 Only Used to set CCR

21 Multiply mul; RegD = RegA * RegB ldaa#3; RegA = 3 ldab#100; RegB = 100 mul; RegD = 300

22 Divide idiv; RegX = RegD/RegX ; RegD = RegD%RegX ldd#53 ldx#12 idiv; RegX = 4, RegD = 5

23 Shift Operations  asla  asld  asrb  lsra  lsrb  rolaRoll left using C bit from CCR  roraRoll right using C bit from CCR

24 Example C code: int i = 23; PORTA = i >> 2; Assembly Code: LDAD #23 ASRD STAB $00; PORTA is address 0

25 Branch operations bcctarget;Branch to target if C=0 bcstarget;Branch to target if C=1 beqtarget;Branch to target if Z=1 bnetarget;Branch to target if Z=0 bmitarget;Branch to target if N=1 bpltarget;Branch to target if N=0 bratarget;Branch to target always jmptarget;Branch to target always 8-bit signed 16-bit signed

26 More branch instructions  Following instructions must follow a subtract instruction bge,bgt,ble,blt

27 Example if(G2 == G1) isEqual(); Given two variable G1 and G2, write assembly code for the above code: ldaaG1 subaG2 bneskip bsrisEqual skip:

28 Example  Implement the following C code in assembly int main() { int i; byte sum = 12; for(i = 0; i <10; i++) sum = sum + 1; }


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