1. 1 Status of the MICROMEGAS semi-digital HCAL M. Chefdeville, LAPP LC Detector group, Annecy CALICE meeting, CERN, 21/05/2011

2. 2 Overview Reminder of nice properties First 1x1 m 2 prototype Next 1x1 m 2 prototypes Test beam plans CALICE DAQv2 Simulation efforts

3. 3 MICROMEGAS for hadronic calorimetry Pros Large area (CERN workshop, industry) Thin chambers (FE embedded on PCB) High efficiency (>97% @ 1.5 fC thr.) Lowest hit multiplicity (<1.12) Proportional avalanche (number of MIPS/pad) Standard gases (Ar/iso or Ar/CO 2 ) Insensitive to neutrons Low working voltages (<500V) Correction of gas gain for P/T High rate capability (barrel & endcaps) Cons Sparking: protections mandatory ! Chips survive 800 V sparks during HV training. Small signals (25 fC for MIPs): low noise ASICs like GASSIPLEX or MICROROC. 1x1 m 2 chamber for a MICROMEGAS SDHCAL technological prototype

4. 4 Design of the first 1x1 m 2 prototype Active Sensor Unit (ASU) 48x32 cm 2 PCB with - 1536 pads of 1x1 cm 2 - Bulk MICROMEGAS - 24 HARDROC2 ASICs - Spark protections - 2 mm dead edges First 1x1 m 2 prototype 1.2 cm thick chamber with - 5 ASUs + 1 ghost - 1 mm gaps with spacers - gas inlet/outlet - 2 % dead area inside gas volume Assembly takes ~ 1 week Readout by 3 DIF + inter-DIF

5. 5 Experience with HARDROC2 Developed by LAL/Omega Equip Lyon GRPC DHCAL PCBs Circuitry - 64 channels - Preamp. with individual gains - 3 thresholds for all channels - Power-pulsing & self-triggering - Fast shaping MICROMEGAS case - single channel noise on ASU ~ 1 fC - chip threshold ~ 12 fC (5*noise + pedestal dispersion) - Signal (25 fC) longer than shaping time, so ~ 10 % signal useful! Threshold settings is CRITICAL Calibration Measure channel pedestal & preamp. gain (DAC/fC) Correct pedestal dispersion with individual preamp. Gains Final threshold of ~ 6 fC Raw Scurves After calibration

6. 6 Test with muons CERN SPS/H4 – June/July 2010 150 GeV/c muons Telescope + 1x1 m 2 prototype With lowest threshold settings and using 10 % of the 25 fC MIP charge - Best efficiency of 43 % - Multiplicity of ~ 1.05 - Max noise probability / trigger ~ 10 -5 Position scan Efficiency depends mainly on threshold not on position (close to spacers, edges, centre...) Run with power pulsing of analogue parts of all HR2 chips During SPS spill which corresponds to ~ 3 A T(ON-OFF) = 2-10 ms No significant effect on efficiency Power pulsing

7. 7 Test in showers (I) CERN/PS/T7-9 - Oct/Nov 2010 Up to 10 GeV/c hadrons Join (with T3B) AHCAL TB Last layer (#31) inside W-structure We wanted to use the AHCAL data in our analysis MICROMEGAS is slower than AHCAL A Synchronisation was needed: - MICROMEGAS records an event ONLY if AHCAL does - 2 DIFs for AHCAL and MICROMEGAS with trigger counters Debugged and functional 2 days before the end of TB About 2.10 6 triggers recorded (10 6 at -10 GeV/c) Will be useful for future combined TBs MANY THANKS to P. Dauncey and G. Vouters + AHCAL group

8. 8 Test in showers (II) Standalone data Nhit in MICROMEGAS chamber increases with energy Hit profile shows muons and EM and H components Combined data Implement DIF counter in lcio converter (Roman, LAL) Reconstruction of AHCAL runs with DIF counter (Angela, CERN) Create AHCAL class in MICROMEGAS framework (Jean, LAPP)

9. 9 Test in showers (III) Event displays: MIPs Apply cut on AHCAL data of 0.6 MIP No energy color code for AHCAL data to better visibility Hit in MICROMEGAS layer ! Synchronisation works ! Linear correlation of MIP position in AHCAL and MICROMEGAS

10. 10 Test in showers (IV) Event displays: Showers Apply cut on AHCAL data of 1 MIP No energy color code for AHCAL data to better visibility Hits in MICROMEGAS layer ! On-going analysis (-10 GeV/c data) Nhit versus shower start layer (longitudinal profile) Nhit versus distance from shower axis (transverse profile)

11. 11 Next 1x1 m 2 prototypes In 2010 - characterisation procedure of ASU established (PCB, Bulk, calibration); - acquisition, reconstruction and analysis software work (LabView & C++); - 1x1 m 2 chambers can be made robust and gas tight; - stable operation in muons and showers - synchronisation for AHCAL-combined TB works; BUT - we need a new ASIC optimised for RO of MICROMEGAS signals MICROROC (R. Gaglione talk) - we need access to PCB components inside 1x1 m 2 chamber Improved chamber design (N. Geffroy)

12. 12 New 1x1 m 2 chamber design Baseplate screwed instead of glued Access to ASIC side of ASUs Gas tightness made by ASU and mask Eventually: get rid of Fe baseplate and improve absorber stiffness (+ 2 mm) ASU mask thickness reduced from 2 to 1 mm Thinner chamber (11 instead of 12 mm) Easier access to DIF connectors and LV & HV patch panel when chambers are inserted inside structures

13. 13 MICROMEGAS ReadOut Chip MICROROC Collaboration between LAPP & LAL/Omega See R. Gaglione talk From HARDROC2 to MICROROC - Same digital part + pin-to-pin compatibility - Current preamp replaced by charge preamp - Additional spark protections inside silicon - Fast shaper (~20ns) replaced by 2 tunable shaper, 30-200 ns - 8 bit preamp gain corrections replaced by 4-bits pedestal corrections Status 350 chips produced, 200 tested, yield of 88 % In principle, enough to equip 2 1x1 m 2 prototypes 7 ASU with 24 chips have been received and cabled: no bugs ! A few ASU equipped with Bulk, all by next week Detailed calibration on-going and test in gas imminent

14. 14 MICROROC ASU test (I) Preamplifier gain 6 ASU, 144 chips, 9216 channels Average all chips ~ 7.1 DAC/fC Compatible with single chip measurements Variations all chips < 2.5 % RMS Variations single chip < 1% RMS Pedestal dispersion Typically 5 DAC units which is about 1 fC Applying pedestal corrections, the dispersion reduces by a factor of 2 Raw Scurve without pedestal correction Raw Scurve with pedestal correction Single chip All chips Single chip

15. 15 MICROROC ASU test (II) Noise level Average all chip ~ 0.12 fC Variations single chip ~ 0.03 fC RMS Detection threshold 5*noise + dispersion leads to ~ 1 fC Should be slightly higher with Bulk: ~ 2 fC Remember: MIP MPV is @ 25 fC ! On-going tests before assembly of 1x1 m 2 prototype HV training First “cooking” went very fast with very few sparks Manufacturing process @ CERN well controlled X-ray and cosmic tests in gas ASU installed in gas box First “real” signals next week ! Single chip All chips

16. 16 Test Beam dates in 2011 (could shift depending on SPS restart date) Prototype assembly beginning June Cosmic test until end of July ASUs for a second prototype ordered Should be available to TB in September Standalone in muon beam, August 3 rd to 21 st in SPS/H4 1 prototype + fine grained telescope Inside absorber structures, Sep/Oct in SPS/H8 2 prototypes inside W structure with synchronisation to AHCAL OR Fe structure with GRPC Lyon DHCAL and CALICE DAQv2

17. 17 LAPP contribution to CALICE DAQv2 Slow Control test Configuration data sent to DIF, loaded into chips, read out back to PC If sent and read out data are the same, SC OK Digital readout test Read out of all ASU chips with one “event” in memory (Start acquisition, 1 trigger, stop acquisition, start readout) Both tests successful with HARDROC, MICROROC, SPIROC Should work with SKIROC CCC LDADCCDIF ASU Ethernet HDMI8b/10b protocole

18. 18 Simulation Studies for SiD - Impact of cracks on HCAL performance - Projective VERSUS non-projective HCAL geometries CALICE note submitted (J. Blaha) - Investigation of alternative geometries Performance with a semi-digital readout - Signal digitisation implemented: Energy, primary statistics, mesh transparency, gas gain, charge thresholds - Optimisation of thresholds for better resolution & linearity on-going

19. 19 Conclusions Several achievements in 2010 First 1x1 m 2 prototype fabricated and tested Several technical choice validated and TB goals reached Important hardware & software development Moving forward with a new FE electronics Smooth transition from HARDROC to MICROROC All ASU for construction of new prototype in hand Assembly in June, TB in August Second MICROROC prototype in September TB in W/Fe structures at the end of the year Sustain simulation efforts HCAL geometries for SiD Performance of semi-digital readout and DAQ developments for CALICE collaboration

20. 20 Acknowledgements LAPP LC Detector group Catherine Adloff Jan Blaha Jean-Jacques Blaising Maximilien Chefdeville Alexandre Dalmaz Cyril Drancourt Ambroise Espargilière Renaud Gaglione Nicolas Geffroy Jean Jacquemier Yannis Karyotakis Fabrice Peltier Julie Prast Guillaume Vouters Collaborators David Attié Enrique Calvo Alamillo Khaled Belkadhi Vincent Boudry Paul Colas Christophe Combaret Rémi Cornat Paul Dauncey Franck Gastaldi Mary-Cruz Fouz Iglesias Wolfgang Klempt Lucie Linsen Rui de Oliveira Dieter Schlatter Nathalie Seguin Christophe de la Taille Wenxing Wang EN-ICE-DEM PH-LCD