1. Progettazione di circuiti e sistemi VLSI Anno Accademico 2007-2008 Lezione 16 Riepilogo 2

2. Sequential Logic 2 storage mechanisms positive feedback charge-based

3. Latch versus Register  Latch stores data when clock is low D Clk Q D Q Register stores data when clock rises Clk D D QQ

4. Latch-Based Design N latch is transparent when  = 0 P latch is transparent when  = 1 N Latch Logic P Latch 

5. Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0D Q 0 1D Q

6. Master-Slave (Edge- Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair

7. Cross-Coupled NAND Cross-coupled NANDs Added clock This is not used in datapaths any more, but is a basic building memory cell

8. Storage Mechanisms D CLK Q Dynamic (charge-based) Static

9. Other Latches/Registers: TSPC Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1)

10. The Design Productivity Challenge Source: sematech97 A growing gap between design complexity and design productivity 1981 Logic Transistors per Chip (K) Productivity (Trans./Staff-Month) 19831985198719891991199319951997199920012003200520072009

11. Design methodologies (general) Three domains –Behavior –Structural –Physic Three levels inside –Architectural –Logic/RTL –Physic

12. Implementation Choices Custom Standard Cells Compiled Cells Macro Cells Cell-based Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Array-based Semicustom Digital Circuit Implementation Approaches

13. Semicustom Design Flow HDL Logic Synthesis Floorplanning Placement Routing Tape-out Circuit Extraction Pre-Layout Simulation Post-Layout Simulation Structural Physical Behavioral Design Capture Design Iteration

14. Prewired Arrays Classification of prewired arrays (or field- programmable devices): Based on Programming Technique –Fuse-based (program-once) –Non-volatile EPROM based –RAM based Programmable Logic Style –Array-Based –Look-up Table Programmable Interconnect Style –Channel-routing –Mesh networks

15. Logic Cell of Actel Fuse-Based FPGA