1. Introduction to Intel IA-32 and IA-64 Instruction Set Architectures

2. The code we used in the class The assembly code is http://www.cs.fsu.edu/~zzhang/CDA3100_Spring_2009_files/first.asm The inline assembly code is: http://www.cs.fsu.edu/~zzhang/CDA3100_Spring_2009_files/tryasm.c

3. 9/27/2007 11:23:26 PMweek06-3.ppt3 History

4. 9/27/2007 11:23:26 PMweek06-3.ppt4 Recent Intel Processors The Intel® Pentium® 4 Processor Family (2000-2006) The Intel® Xeon® Processor (2001-2006) The Intel® Pentium® M Processor (2003-Current) The Intel® Pentium® Processor Extreme Edition (2005- 2007) The Intel® Core™ Duo and Intel® Core™ Solo Processors (2006-Current) The Intel® Xeon® Processor 5100 Series and Intel® Core™2 Processor Family (2006-Current)

5. 9/27/2007 11:23:27 PMweek06-3.ppt5 History

6. 9/27/2007 11:23:27 PMweek06-3.ppt6 Most Recent Intel Processors

7. 9/27/2007 11:23:28 PMweek06-3.ppt7 Intel Core 2 Duo Processors

8. 9/27/2007 11:23:28 PMweek06-3.ppt8 Intel Core 2 Quad Processors

9. 9/27/2007 11:23:29 PMweek06-3.ppt9 Bit and Byte Ordering

10. 9/27/2007 11:23:29 PMweek06-3.ppt10 Intel Assembly Each instruction is represented by – Where label presents the line – A mnemonic is a reserved name for a class of instruction opcodes which have the same function. – The operands argument1, argument2, and argument3 are optional. There may be from zero to three operands, depending on the instruction

11. 9/27/2007 11:23:30 PMweek06-3.ppt11 Memory Modes

12. 9/27/2007 11:23:30 PMweek06-3.ppt12 Addressing The processors use byte addressing Intel processors support segmented addressing – Each address is specified by a segment register and byte address within the segment

13. 9/27/2007 11:23:30 PMweek06-3.ppt13

14. 9/27/2007 11:23:31 PMweek06-3.ppt14 Intel Registers

15. 9/27/2007 11:23:31 PMweek06-3.ppt15 Basic Program Execution Registers General purpose registers – There are eight registers (note that they are not quite general purpose as some instructions assume certain registers) Segment registers – They define up to six segment selectors EIP register – Effective instruction pointer EFLAGS – Program status and control register

16. 9/27/2007 11:23:32 PMweek06-3.ppt16 General Purpose and Segment Registers

17. 17 General Purpose Registers EAX — Accumulator for operands and results data EBX — Pointer to data in the DS segment ECX — Counter for string and loop operations EDX — I/O pointer ESI — Pointer to data in the segment pointed to by the DS register; source pointer for string operations EDI — Pointer to data (or destination) in the segment pointed to by the ES register; destination pointer for string operations ESP — Stack pointer (in the SS segment) EBP — Pointer to data on the stack (in the SS segment)

18. 18 Alternative General Purpose Register Names

19. 19 Registers in IA-64

20. 20 Segment Registers

21. 21 Operand Addressing Immediate addressing – Maximum value allowed varies among instructions and it can be 8-bit, 16-bit, or 32-bit Register addressing – Register addressing depends on the mode (IA-32 or IA-64)

22. 22 Register Addressing

23. 23 Memory Operand Memory operand is specified by a segment and offset

24. 24 Offset Displacement - An 8-, 16-, or 32-bit value. Base - The value in a general-purpose register. Index — The value in a general-purpose register. Scale factor — A value of 2, 4, or 8 that is multiplied by the index value.

25. 25 Effective Address

26. 26 Effective Address Common combinations – Displacement – Base – Base + displacement – (Index * scale) + displacement – Base + index + displacement – Base + (Index * scale) + displacement

27. 27 Addressing Mode Encoding

28. 28 Fundamental Data Types

29. 29 Example

30. 30 Pointer Data Types Near pointer Far pointer

31. 31 128-Bit SIMD Data Types

32. 32 BCD Integers Intel also supports BCD integers, where each digit (0-9) is represented by 4 bits

33. 33 Floating Point Numbers

34. 34 General Purpose Instructions Data transfer instructions

35. 35 Data Transfer Instructions

36. 36 Data Transfer Instructions

37. 37 Binary Arithmetic Instructions

38. 38 Decimal Arithmetic Instructions

39. 39 Logical Instructions

40. 40 Shift and Rotate Instructions

41. 41 Bit and Byte Instructions

42. 42 Bit and Byte Instructions

43. 43 Control Transfer Instructions

44. 44

45. 45 String Instructions

46. 46 I/O Instructions These instructions move data between the processor’s I/O ports and a register or memory

47. 47 Enter and Leave Instructions These instructions provide machine-language support for procedure calls in block structured languages

48. 48 Segment Register Instructions The segment register instructions allow far pointers (segment addresses) to be loaded into the segment registers

49. 49 Procedure Call Types The processor supports procedure calls in the following two different ways: – CALL and RET instructions. – ENTER and LEAVE instructions, in conjunction with the CALL and RET instructions

50. 50 Stack

51. 51 Calling Procedures Using CALL and RET Near call (within the current code segment) Near return

52. 52 Far Call and Far Return Far call Far return

53. 53 Stack During Call and Return

54. 54 Parameter Passing Passing parameters through the general-purpose registers – Can pass up to six parameters by copying the parameters to the general-purpose registers Passing parameters on the stack – Stack can be used to pass a large number of parameters and also return a large number of values Passing parameters in an argument list – Place the parameters in an argument list – A pointer to the argument list can then be passed to the called procedure

55. 55 Saving Procedure State Information The processor does not save general purpose registers – A calling procedure should explicitly save the values in any of the general-purpose registers that it will need when it resumes execution after a return – One can use PUSHA and POPA to save and restore all the general purpose registers (except ESP)

56. 56 Calls to Other Privilege Levels

57. 57 Stack For Calling and Called Procedure

58. 58 Procedure Calls For Block-structured Languages ENTER and LEAVE instructions automatically create and release, respectively, stack frames for called procedures – The ENTER instruction creates a stack frame compatible with the scope rules typically used in block-structured languages – The LEAVE instruction, which does not have any operands, reverses the action of the previous ENTER instruction

59. 59 ENTER Instruction

60. 60 IA-32 and IA-64 Instruction Format

61. 61 Examples of Instruction Formats

62. 62 ADD Instructions

63. 63 ADD Instructions

64. 64 Add Instruction Description

65. 65 SCAS/SCASB/SCASW/SCASD—Scan String

66. 10/7/2007 9:37:48 PMweek07-1.ppt66 SIMD in IA-32 and IA-64 To improve performance, Intel adopted SIMD (single instruction multiple data) instructions – MMX technology (Pentium II processor family) – SSE

67. 10/7/2007 9:37:59 PMweek07-1.ppt67 MMX MMX introduced – Eight new 64-bit data registers, called MMX registers – Three new packed data types: 64-bit packed byte integers (signed and unsigned) 64-bit packed word integers (signed and unsigned) 64-bit packed double word integers (signed and unsigned) – Instructions that support the new data types

68. 10/7/2007 9:38:00 PMweek07-1.ppt68 MMX Packed integer types allow operations to be applied on multiple integers

69. 10/7/2007 9:38:04 PMweek07-1.ppt69 SSE SSE introduced eight 128-bit data registers (called XMM registers) – In 64-bit modes, they are available as 16 64-bit registers – The 128-bit packed single-precision floating-point data type, which allows four single-precision operations to be performed simultaneously They can be used in parallel with MMX registers

70. 10/7/2007 9:38:04 PMweek07-1.ppt70 SSE Execution Environment

71. 10/7/2007 9:38:05 PMweek07-1.ppt71 XMM Registers In certain modes, additional eight 64 bit registers are also available (XMM8 - XMM15)

72. 10/7/2007 9:38:05 PMweek07-1.ppt72 SSE Data Type SSE extensions introduced one new data type – 128-Bit Packed Single-Precision Floating-Point Data Type – SSE 2 introduced five data types

73. 10/7/2007 9:38:07 PMweek07-1.ppt73 P acked and Scalar Double-Precision Floating-Point Operations

74. 10/7/2007 9:38:10 PMweek07-1.ppt74 SSE Instructions SSE Data Transfer Instructions

75. 10/7/2007 9:38:11 PMweek07-1.ppt75 SSE Packed Arithmetic Instructions

76. 10/7/2007 9:38:12 PMweek07-1.ppt76 SSE Packed Arithmetic Instructions

77. 10/7/2007 9:38:12 PMweek07-1.ppt77 SSE Comparison, Logical, and Shuffle Instructions

78. 10/7/2007 9:38:14 PMweek07-1.ppt78 SSE2 Instructions

79. 10/7/2007 9:38:14 PMweek07-1.ppt79 SSE2 128-Bit SIMD Integer Instructions

80. 10/7/2007 9:38:16 PMweek07-1.ppt80 Horizontal Addition/Subtraction

81. 10/7/2007 9:38:17 PMweek07-1.ppt81 Horizontal Data Movements

82. 10/7/2007 9:38:17 PMweek07-1.ppt82 Conversion Between Different Types

83. 10/7/2007 9:38:18 PMweek07-1.ppt83 Using MMX/SSE Instructions in C/C++ Programs Data types for MMX and SSE instructions – These types are defined in C/C++ /usr/lib/gcc/i386-redhat-linux/3.4.3/include/mmintrin.h /usr/lib/gcc/i386-redhat-linux/3.4.3/include/pmmintrin.h /usr/lib/gcc/i386-redhat-linux/3.4.3/include/emmintrin.h

84. 10/7/2007 9:38:29 PMweek07-1.ppt84 Built-in Functions Built-in functions are C-style functional interfaces to MMX/SSE instructions See http://developer.apple.com/documentation/DeveloperTools/gcc-4.0.1/gcc/X86-Built_002din-Functions.html

85. 10/7/2007 10:01:41 PMweek07-1.ppt85 Intel MMX/SSE Intrinsics Intrinsics are C/C++ functions and procedures for MMX/SSE instructions – With instrinsics, one can program using these instructions indirectly using the provided intrinsics – In general, there is a one-to-one correspondence between MMX/SSE instructions and intrinsics

86. 10/7/2007 10:01:43 PMweek07-1.ppt86 GCC Inline Assembly GCC inline assembly allows us to insert inline functions written in assembly – GCC provides the utility to specify input and output operands as C variables – Basic inline – Extended inline assembly

87. 10/7/2007 10:03:01 PMweek07-1.ppt87 GCC Inline Assembly Some examples

88. 10/7/2007 10:03:04 PMweek07-1.ppt88 GCC Inline Assembly

89. 10/7/2007 10:03:06 PMweek07-1.ppt89 GCC Inline Assembly