1. CORE Lab. E.E. 1 Soft timers : efficient microsecond so ftware timer support for network proc essing Mohit Aron and Peter Druschel 17 th ACM Symposium on Operating Systems Pri nciples 11.23 2000 Sang Seok Lim

2. CORE Lab. E.E. 2 Introduction H/W Timer –High priority : interrupt based –8253 chipset –Overhead : context switching and memory locality S/W Timer –Low cost : trigger state –Microseconds granularity –Rate-based transmission & network polling

3. CORE Lab. E.E. 3 Motivation Modern CPUs : Pipelining and caching –Sensitive to unpredictable control transfer Interrupt and context switching –msec order is not a concern DISK, time quantum –High speed Network : microsecond order Overhead in H/W timer –Context switching Saving and restoring CPU state Memory access locality shift : Cache and TLB misses

4. CORE Lab. E.E. 4 Soft Timers Trigger states –Event handler could be invoked with minimal overhead –Examples At the end of system call At the end of exception handler At the end of interrupt handler CPU is executing the idle loop –Invoking a handler in trigger state No more than a function call

5. CORE Lab. E.E. 5 Cont ’ d Operation –In trigger state : Check any pending soft timer events Invokes the associated handlers Advantage –Without incurring the cost of a H/W timer interrupt Disadvantage –Event handler may be delayed(probabilistically) –Maximal delay is bounded(periodic H/W interrupt) Soft timer granularity –Tens of microsecs

6. CORE Lab. E.E. 6 Cont ’ d Soft timer facility –measure_resolution() –measure_time() –schedule_soft_event(T,handler) –interrupt_clock_resolution()

7. CORE Lab. E.E. 7 Cont ’ d Random variable

8. CORE Lab. E.E. 8 Application of soft timers Rated-based clocking –TCP perform rate-based clocking –For preventing bursty packet transmission Simple algorithm with two parameters –Target transmission rate –Maximal allowable burst transmission rate Network Polling –Network interrupt : at a rate of tens of microseconds –Polling with status registers Avoid overhead of interrupt Reduce the impact of memory access locality shift –Increase communication latency : Hybrid approach

9. CORE Lab. E.E. 9 Experimental Results Four 300MHz Pentium-II 128MB of RAM Apache-1.3.3 Repeatedly requested 6Kbyte file -> saturated H/W timer with null handler Soft timer-> NO throughput degradation!!!

10. CORE Lab. E.E. 10 Cont ’ d Soft timer event granularity under different workloads

11. CORE Lab. E.E. 11 Cont ’ d

12. CORE Lab. E.E. 12 Four 300MHz Pentium-II 128MB of RAM Apache-1.3.3 Repeatedly requested 6Kbyte file -> saturated H/W timer with null handler

13. CORE Lab. E.E. 13

14. CORE Lab. E.E. 14

15. CORE Lab. E.E. 15

16. CORE Lab. E.E. 16 Conclusion & Critiques Conclusion –Soft timer using trigger State –Eliminate overhead of interrupt based timer Context switch and interrupt –Increase communication latency Hybrid approach –Efficiently applicable to rate-based clocking and polling Critiques –Don ’ t talk about Communication latency detailed –Application dependent Real time system Multimedia server