1. Timers Presented by: Griffin Reid Rohit Vardhan Freddie Wilson Date: October 25, 2005

2. 2 Overview Introduction Timer –Counter –Prescaler Periodic Interrupts or Real Time Interrupts Input Capture Output Compare Pulse Accumulators Applications of Timer functions

3. 3 Introduction - Definition A timer is an oscillator that vibrates at a precise and programmable frequency Timers are used when we want something to happen after a fixed interval of time Example – alarm clocks, digital cameras and “The Whistle”

4. 4 Introduction – HC11 Timer Built in timer in one of the Integrated Circuits (IC). Frequency is 2 MHz or Time period is 0.5 μs. Timer Counter (16 bit counter) and Prescaler (sets frequency of counter) Real Time Interrupts – generates interrupts at a fixed periodic rate Input Capture – Record time after a selected transition is detected at a timer input pin Output Compare – Generate output signals and timing software delays Pulse Accumulators (8 bit counter)

5. 5 HC11 – Timer ports In the HC11, Port A pin control block includes logic for timer functions –PA0~PA2, input-only, serves as IC3~IC1 –PA3, bidirectional, serves as IC4 or OC5 (determined by PACTL ($1026) I4/O5 bit) or general purpose I/O (determined by DDRA3 bit of PACTL) –PA4~PA6, output only, serves as OC4~OC2 –PA7, bidirectional, serves as input to pulse accumulator (special OC1) or general purpose I/O (determined by PACTL DDRA7 bit)

6. 6 Timer Counter Central element: 16-bit free running counter Starts as soon as HC11 is reset from $0000 and increases by 1 every cycle After reaching $FFFF, counter rolls back to $0000 and the overflow bit is set Can be read at any time using a 2 byte instruction like LDD or LDX Cannot be written or reset during operation

7. 7 Timer Overflow Timer overflow flag (TOF) status bit is set each time the counter rolls over from $FFFF to $0000 TOF status bit can generate an automatic interrupt request by setting the timer overflow interrupt (TOI) enable bit The interrupt is generated by writing the memory location of the first line of code to be executed in the Timer Overflow Jump Vectors

8. 8 Timer – Jump Vectors Table 4. Buffalo Monitor Interrupt Jump Table (Pg 23) of the EVB Manual $00D0-$00D2 Timer Overflow $00EB-$00ED Real Timer Interrupt $00D3-$00D5 Timer Output Compare 5 Example 7E 10 53 7E is the JMP command

9. 9 Clearing Timer Flags Load an accumulator with a mask that has a one in the bit(s) corresponding to the flag(s) to be cleared Then write this value to TFLG1 or TFLG2 –Example- LDAA #$80, STAA TFLG2 will clear TOF OR use BCLR instruction to clear the flag, the mask should have zeroes in the bit positions corresponding to the flags to be cleared and ones in all other bits. –Example- BCLR TFLG2 #%01111111

10. 10 Clearing Timer Flags (…contd) Caution ! –Do not use BSET to clear flags –Because it could inadvertently clear one or more of the other flags in the register

11. 11 Timer Prescaler Allows 4 clocking rates of the timer counter –E-clock rate divided by: 1, 4, 8 and 16 At reset, the default prescale factor is 1 Must be set during the first 64 E-Clock cycles after reset

12. 12 Prescaler settings Trade-off between timer resolution and timer range

13. 13 Real-Time Interrupts Generates hardware interrupts at a fixed rate Source for the RTI function is a free-running clock that cannot be stopped or interrupted One of four rates has to be selected Flag is set at user determined rate Flag must be cleared after it is used, or interrupts will occur periodically and system may hang up

14. 14 RTI Registers TMSK2 $1024 –Real-time Interrupt Enable TFLG2 $1025 –Real-time Interrupt Flag PACTL $1026 –Real-time Interrupt Rate Select

15. 15 RTI Rate Select For 8 MHz Crystal Frequency or 2MHz E Clock RTR1RTR0E/213 Divided byNominal RTI Rate 0014.10 ms 0128.19 ms 10416.38 ms 11832.77 ms

16. 16 Example of Timers Closed Loop DC motor control Set the counter range Check motor speed after counter overflows Store value in a global variable Compare experimental motor speed (ω ex ) to theoretical motor speed (ω th ) –Increase motor speed if ω ex < ω th –Decrease motor speed if ω ex > ω th

17. 17 Input Capture Used to record the time an external event occurs Accomplished by recording the contents of the free-running counter when a selected edge is detected at the related timer input pin The time is saved in the input capture register

18. 18 Overview Measure as short as one timer count periods by connecting the signal to two IC pins Software limits the minimum period that can be detected when using one IC pin Measuring periods longer than counter range by counting overflow

19. 19 Registers Contents of the free-running counter are stored in the input capture registers when an edge is detected The registers are 16-bit and read only Bit 15 - Bit 8 Bit 7Bit 0 TIC1H $1011 $1010 Bit 15Bit 8 Bit 7Bit 0 TIC2L$1013 $1012 Bit 15Bit 8 Bit 7Bit 0 TIC3H $1015 $1014 ----- ------ ------ ------ ------ ------ TIC1L TIC2H TIC3L

20. 20 Registers Registers operate independently of each other –They can operate simultaneously Read of high-order bytes of a TIC register inhibits a new capture transfer for one bus cycle (to make sure the captured two bytes belong with each other) Inhibited capture will be delayed but will not be lost

21. 21 Configuration EDGxBEDGxA Capture Disabled00 Capture on Rising Edge Only01 Capture on Falling Edge Only10 Capture on Any Edge11 EDG3A TCTL2$1021 01234567 EDG3BEDG2AEDG2BEDG1AEDG1BEDG4AEDG4B Which edge to capture on can be configured with the TCTL2 register

22. 22 Flags and Interrupts Flags are set when a capture is made Interrupts can be generated if the mask bits are set OC1FOC2F IC3F TFLG1$1023 OC3FOC4FOC5F IC1FIC2F 01234567 OC1IOC2I IC3I TMSK1$1022 OC3IOC4IOC5I IC1IIC2I 01234567

23. 23 Example Program Reference Manual pg. 394

24. 24 Applications Measure signal period/frequency –By capturing successive edges with same polarity Measure pulse width –By capturing successive edges with alternate polarity Record the time at which some external event occurred

25. 25 Output Compare Used for outputting waveforms or is used for time delays Accomplished by comparing the contents of the free-running counter with the compare register When a match occurs an output is generated

26. 26 Overview There are 5 output compare functions OC1-OC5 Each has 16-bit compare register and comparator The registers are compared to the free-running timer value every timer count When there is a match a status flag is set, an interrupt can be generated The comparison is done in hardware – basically free computing time

27. 27 Flags and Interrupts When Output Compare is successful it sets corresponding Flag in TFLG1 Control Register: OC1FOC2FOC3FOC4FOC5F IC1F IC2FIC3F TFLG1 $1023 Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5 OC1IOC2IOC3IOC4IOC5I IC1I IC2IIC3I TMSK1 $1022 Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5 It can also generate an interrupt if the appropriate mask bits are set

28. 28 Output Compare Pins For Output Compare OC2-OC5, Each Compare register control is associated with a separate pin TCTL1 register controls the automatic action that will occur at the respective timer output pin when there is a successful output compare match Output Compare 2PA6 Output Compare 3PA5 Output Compare 4PA4 Output Compare 5PA3 OM2OL2OM3OL3OM4OL4OM5OL5 $1020 OMxOLxPin Configuration 00Do nothing to pin 01Toggle pin on match 10Clear pin on match 11Set pin on match TCTL1

29. 29 Output Compare 1 Allows one output compare to simultaneously control the states of up to five output pins Can also be configured to control pin(s) that are being controlled by one of the other four OC functions (OC1 has priority when compares occur at the same time) Pin actions are controlled by the OC1M specifies which port A outputs are to be used OC1M7OC1M6OC1M5OC1M4OC1M3000 OC1M Register determines which Port A Pins will be Controlled by Output Compare 1 OC1D7OC1D6OC1D5OC1D4OC1D3000 OC1D Register sets value to be written to Port A pins selected in OC1M PA7PA6PA5PA4PA3 OC1M $100C OC1D $100D

30. 30 Forced Output Compare Uses of force output compare –Set an initial state at the start of a timing sequence –Output compare earlier than it was scheduled Actions taken as a result of a forced compare is the same as if there were a match btw the OCx and the TCNT, except that the corresponding interrupt status flag bits are not set

31. 31 Applications Program an action to occur at a specific time Produce a pulse of specific duration Generate a specific delay

32. 32 Pulse Accumulator Is an 8-bit counter/timer system Can be written to, unlike the Timer counter Can act as an event counter Can act as an E/64 clock Is associated with two maskable interrupts

33. 33 External Event Counter Counts how many times something happens Can count rising edges or falling edges of sensor output An example would be counting how many times a door was opened

34. 34 External Event Counter To count more than 256 events the software will have to keep a record of how many time the accumulator overflowed The Pulse accumulator can be set to interrupt the program after N number of events by writing the two’s compliment of N to the PACNT register

35. 35 Gated Time Accumulation (E/64 clock) The clock counts as long as the PAI pin of the TMSK2 is active. The PEDGE bit of the PACTL register determines if the PAI pin is active when high or low This mode can be used to record how much time the pin was active or the duration of a singles pulse For example this can be used to see how long a door stays open.

36. 36 Gated Time Accumulation (E/64 clock) Time can be measured past the 8-bit counter using the software to keep track of overflows The PAI can be used as an input edge interrupt that is activated by a high or low signal

37. 37 PACTL Register DDRA7 –Set to 0 for PA7 input –Set to 1 for PA7 output PAEN –Set to 0 to disable Pulse accumulator –Set to 1 to enable Pulse accumulator Address:$1026 Bit 7654321Bit 0 Read DDRA7PAENPAMODPEDGE00RTR1RTR0 Write: Reset00000000

38. 38 PACTL Register PAMOD –Set to 0 for external event counting mode –Set to 1 for E/64 clock mode PEDGE –Set to 0 to make Pulse accumulator respond to falling edges –Set to 1 to make Pulse accumulator respond to rising edges Address:$1026 Bit 7654321Bit 0 Read DDRA7PAENPAMODPEDGE00RTR1RTR0 Write: Reset00000000

39. 39 TFLG2 Register PAOVF –Pulse accumulator overflow interrupt flag. PAIF –Pulse accumulator input edge interrupt flag Address:$1025 Bit 7654321Bit 0 Read TOFRTIFPAOVFPAIF0000 Write: Reset00000000

40. 40 TMSK2 Register PAOVI –Pulse accumulator overflow interrupt enable bit PAII –Pulse accumulator input edge interrupt enable bit Address:$1024 Bit 7654321Bit 0 Read TOIRTIIPAOVIPAII00PR1PR0 Write: Reset00000000

41. 41 PACNT Register Pulse accumulator count register Write two’s compliment of N to PACNT to get an overflow interrupt after N counts Address:$1027 Bit 7654321Bit 0 Read Bit 7654321Bit 0 Write: Reset00000000

42. 42 Pulse Accumulator Interrupts When a Pulse accumulator overflow interrupt occurs, the HC11 jumps to $00CD-$00CF to find the memory location of the subroutine to run. When a Pulse accumulator input edge interrupt occurs, the HC11 jumps to $00CA-$00CC to find the memory location of the subroutine to run.

43. 43 References 1. M68HC11E Series Programming Reference Guide Rev. 2 10/2003 2. M68HC11 Reference Manual Rev. 6 4/2002 3. CME11E9-EVBU Manual