1. FW and HW Status TDAQ WG 10/6/2015

2. Hardware MPOD: ◦ HV was NOT floating   Sensibility of current limit to external devices  Particularly for chamber 4 close to RICH  We have seen more problems on this chamber (no systematic studies has been performed)  Possible extra noise?  Cover links  Could influence stability  Famous glitches (1 or 2 per day)? 2

3. Hardware SRB: ◦ All SRBs has been patched in order to be able to use the NIM in/out features (April) ◦ SRBs tested in 154 (May):  Specific test bench has been installed, 16 covers and MPOD (mini) ◦ Boards re-installed and cabled in ECN3 3

4. Firmware (Cover) Version 15 ◦ Used during the Pilot Run Version 16 (new) ◦ Improve link usage  Remove 1 clock cycle gap between data ◦ Improve data multiplexing  Use round-robin instead of circular full scan ◦ “password on everything” not done  Link problem probably due to MPOD HV not floating  Wait for tests ◦ Not yet compiled ◦ Supposed to start the test last week (illness) 4

5. Firmware (SRB) Work was not only the trigger matching. The FW is now more stable: fixing bugs and weak points consolidation were part of the “restyling”. Common to all FPGAs: ◦ 2.5Gb/s links:  ALTERA IP core bug in internal parameter settings causing link instability  We have seen links failing in 2014 run  Error in startup conditions causing bytes swapping during configuration  One of the most frequent problems 5

6. Firmware (SRB) Fe_intf version 7 : ◦ Only common problem above Trig_mgr version 4 : ◦ Fixed wrong clock for TTCrx interface configuration  Could be the source of T0 delay problem, need to test ◦ Added L0ID and trigger_type generation  Fast link is used to transfer to event_mgr and vme_bm Event_mgr version 3 : ◦ Fix data writing from fe_intf - only when links are aligned  Could have caused data corruption at the start of the burst ◦ Added L0ID and trigger_type reception ◦ Time-reordering and trigger-matching  Interface to Ethernet missing  Buffer selection missing Supposed to start the test last week (illness) 6

7. Firmware Ethernet interface Event Storage Event Event Storage Event Event Storage Event Event Storage Event ETH 0 ETH 1 TRG_fifo DATA_fifo CNT_fifo TRIGGER MATCHING Max 16 events per packet 7

8. Firmware (Ethernet Interface) Event Storage Event Event Storage Event Event Storage Event Event Storage Event ETH 0 ETH 1 TRG_fifo DATA_fifo CNT_fifo TRIGGER MATCHING 8

9. Current Limitations 1 packet per PC Max 16 events per packet 1 Ethernet port supported NO fragmentation NO tuning of trigger time window offset 9

10. Conclusions and Plans Hardware: ◦ Ready for the upcoming RUN ◦ MPOD trip problem is not yet understood (1 or 2 trips per day is still acceptable?) Firmware: ◦ SRB is almost ready to be tested (needs finalization) ◦ COVER version 16 should be tested this week Next step(s): ◦ Test in the lab to assure that the firmware is behaving as expected ◦ Move to ECN3 in order to take part to the NA62 DAQ and RUN control ◦ Debugging (of course…) ◦ 0 biassed VME data transmission 10