1. CMX firmware development Pawel Plucinski Stockholm University Stockholm University CMX firmware status G-Link and GTX serializer Clock manager Memory Conclusions

2. CMM code – the port to the V6 Recent changes and tests Two versions: VC and VS. G-link emulation + serializer GTX (including ISIM and scope tests of the optical output; target ML605 - xc6vlx240t). Adapting the clock tree to the Virtex-6 MMCM. Updating the block RAM implementation in the readout fifo/memory. Successfully simulated (ISIM). CMM code – the port to the V6. This includes:

3. G-link emulation in Virtex 6 General idea G-link encoder GTX TX 24b  8b multiplexer DAV (data available) DAQ or ROI data word 20b Encoded word 960 Mbs 40 MHz 120 MHz 24b 8b

4. G-link emulation in Virtex 6 The readout scheme G-link encoder GTX TX DAQ_IN DAQ_DAV G-link encoder GTX TX DAQ_RST ROI_IN ROI_RST 20b ROI_DAV clk120 clk40 Mux clk40 clk120 clk40 clk120 daq_enc roi_enc 24b roi_byte 8b daq_bytedaq_out roi_out 2b

5. G-link emulation in Virtex 6 Behavioral simulation results Reset DAV asserted Empty frames Sending zeros non zeros data This test was done with Xilinx ISIM...

6. G-link emulation in Virtex 6 “An eye diagram” Good result: Rise and Fall time below 240 psec! Scope tests of the optical output (target ML605):

7. CMM code – the port to the V6 Adapting the clock tree (MMCM)

8. CMM code – the port to the V6 Updating the block RAM Memory type: True Dual Port RAM Write/Read Width:16b Write/Read Depth:256

9. CMM code – the port to the V6 Simulation results: cmm_jepcrt_vc Testbench with random input data (no errors). No errors DAQ data

10. CMM code – the port to the V6 Simulation results: cmm_jepcrt_vs Testbench with random input data (no errors). No errors DAQ and ROI data Readout enable

11. Conclusion 'Jet-CMM emulation' design for Virtex-6 on the CMX: two versions 'vc' and 'vs', available on SVN. G-link protocol + GTX serializer is added The Clock tree is updated. The clock manager (MMCM) is being used. 'A new block RAM' in the readout fifo/memory implemented. Design was successfuly simulated with ISIM (testbunch, random input data, no errors). Latency is unchanged.