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Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 6-1 Chapter 6: Hierarchical.

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Presentation on theme: "Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 6-1 Chapter 6: Hierarchical."— Presentation transcript:

1 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-1 Chapter 6: Hierarchical Structural Modeling Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology

2 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-2 Module Definitions // port list style module module_name [#(parameter_declarations)][port_list]; parameter_declarations; // if no parameter ports are used port_declarations; other_declaration; statements; endmodule // port list declaration style module module_name [#(parameter_declarations)][port_declarations]; parameter_declarations; // if no parameter ports are used other_declarations; statements; endmodule

3 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-3 Port Declarations  Three types  input  output  inout module adder(x, y, c_in, sum, c_out); input [3:0] x, y; input c_in; output reg [3:0] sum; output reg c_out;

4 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-4 Types of Parameters  module parameters  parameter  localparam  specify parameters parameter SIZE = 7; parameter WIDTH_BUSA = 24, WIDTH_BUSB = 8; parameter signed [3:0] mux_selector = 4’b0;

5 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-5 Constants Specified Options  `define compiler directive `define BUS_WIDTH 8  Parameter parameter BUS_WIDTH = 8;  localparam localparam BUS_WIDTH = 8;

6 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-6 Parameter Ports module module_name #(parameter SIZE = 7, parameter WIDTH_BUSA = 24, WIDTH_BUSB = 8, parameter signed [3:0] mux_selector = 4’b0 ) (port list or port list declarations)... endmodule

7 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-7 Module Instantiation  Syntax module_name [#(parameters)] instance_name [range]([ports]); module_name [#(parameters)] instance_name [{,instance_name}]([ports]);

8 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-8 Port Connection Rules  Named association.port_id1(port_expr1),...,.port_idn(port_exprn)  Positional association port_expr1,..., port_exprn

9 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-9 Parameterized Modules  An example module adder_nbit(x, y, c_in, sum, c_out); parameter N = 4; // set default value input [N-1:0] x, y; input c_in; output [N-1:0] sum; output c_out; assign {c_out, sum} = x + y + c_in; endmodule

10 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-10 Module Parameters Values  Ways to change module parameters values  defparam statement  module instance parameter value assignment

11 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-11 Overriding Parameters  Using the defparam statement // define top level module … output [3:0] qout4b; output [7:0] qout8b; // instantiate two counter modules defparam cnt_4b.N = 4, cnt_8b.N = 8; counter_nbits cnt_4b (clock, clear, qout4b); counter_nbits cnt_8b (clock, clear, qout8b); module counter_nbits (clock, clear, qout); parameter N = 4; // define counter size … always @(negedge clock or posedge clear) begin // qout <= (qout + 1) % 2^n if (clear) qout <= {N{1'b0}}; else qout <= (qout + 1) ; End

12 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-12 // define top level module … output [3:0] qout4b; output [7:0] qout8b; // instantiate two counter modules counter_nbits #(4) cnt_4b (clock, clear, qout4b); counter_nbits #(8) cnt_8b (clock, clear, qout8b); Overriding Parameters  Using module instance parameter value assignment--- one parameter module counter_nbits (clock, clear, qout); parameter N = 4; // define counter size … always @(negedge clock or posedge clear) begin // qout <= (qout + 1) % 2^n; if (clear) qout <= {N{1'b0}}; else qout <= (qout + 1) ; end

13 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-13 Overriding Parameters  Using module instance parameter value assignment --- two parameters // define top level module module … … hazard_static #(4, 8) example (x, y, z, f); module hazard_static (x, y, z, f); parameter delay1 = 2, delay2 = 5; … and #delay2 a1 (b, x, y); not #delay1 n1 (a, x); and #delay2 a2 (c, a, z); or #delay2 o2 (f, b, c); endmodule hazard_static #(.delay2(4),.delay1(6)) example (x, y, z, f); parameter value assignment by name --- minimize the chance of error!

14 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-14 Hierarchical Path Names  An identifier can be defined within  Modules  Tasks  Functions  Named blocks (See Section 7.1.3)  Hierarchical path names 4bit_adder // top level --- 4bit_adder 4bit_adder.fa_1 // fa_1 within 4bit_adder 4bit_adder.fa_1.ha_1 // ha_1 within fa_1 4bit_adder.fa_1.ha_1.xor1 // xor1 within ha_1 4bit_adder.fa_1.ha_1.xor1.S // net s within xor1

15 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-15 generate Block Structures  The keywords used  generate and endgenerate // convert Gray code into binary code parameter SIZE = 8; input [SIZE-1:0] gray; output [SIZE-1:0] bin; genvar i; generate for (i = 0; i < SIZE; i = i + 1) begin: bit assign bin[i] = ^gray[SIZE-1:i]; end endgenerate

16 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-16 The generate Loop Construct // convert Gray code into binary code parameter SIZE = 8; input [SIZE-1:0] gray; output [SIZE-1:0] bin; reg [SIZE-1:0] bin; genvar i; generate for (i = 0; i < SIZE; i = i + 1) begin:bit always @(*) bin[i] = ^gray[SIZE - 1: i]; end endgenerate

17 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-17 An n-bit Adder // define a full adder at dataflow level. module full_adder(x, y, c_in, sum, c_out); // I/O port declarations input x, y, c_in; output sum, c_out; // Specify the function of a full adder. assign {c_out, sum} = x + y + c_in; endmodule

18 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-18 An n-bit Adder module adder_nbit(x, y, c_in, sum, c_out); … genvar i; wire [N-2:0] c; // internal carries declared as nets. generate for (i = 0; i < N; i = i + 1) begin: adder if (i == 0) // specify LSB full_adder fa (x[i], y[i], c_in, sum[i], c[i]); else if (i == N-1) // specify MSB full_adder fa (x[i], y[i], c[i-1], sum[i], c_out); else // specify other bits full_adder fa (x[i], y[i], c[i-1], sum[i], c[i]); end endgenerate

19 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-19 An n-bit Adder module adder_nbit(x, y, c_in, sum, c_out); … genvar i; wire [N-2:0] c; // internal carries declared as nets. generate for (i = 0; i < N; i = i + 1) begin: adder if (i == 0) // specify LSB assign {c[i], sum[i]} = x[i] + y[i] + c_in; else if (i == N-1) // specify MSB assign {c_out, sum[i]} = x[i] + y[i] + c[i-1]; else // specify other bits assign {c[i], sum[i]} = x[i] + y[i] + c[i-1]; end endgenerate

20 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-20 An n-bit Adder module adder_nbit(x, y, c_in, sum, c_out); … genvar i; reg [N-2:0] c; // internal carries declared as nets. generate for (i = 0; i < N; i = i + 1) begin: adder if (i == 0) // specify LSB always @(*) {c[i], sum[i]} = x[i] + y[i] + c_in; else if (i == N-1) // specify MSB always @(*) {c_out, sum[i]} = x[i] + y[i] + c[i-1]; else // specify other bits always @(*) {c[i], sum[i]} = x[i] + y[i] + c[i-1]; end endgenerate

21 Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 6-21 A UDP Example // an example of sequential UDP instantiations parameter N = 4; input clk, clear; output [N-1:0] qout; …. genvar i; generate for (i = 0; i < N; i = i + 1) begin: ripple_counter if (i == 0) // specify LSB T_FF tff (qout[i], clk, clear); else // specify the rest bits T_FF tff (qout[i], qout[i-1], clear); end endgenerate

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