1. Static DLX processor Understanding its architecture and available toolset

2. Available Tools C compiler Assembler tim2vhdl timtool

3. C compiler A C compiler for this DLX processor is generated using the retargetable C compiler lcc which was created at Princeton. The url for lcc is http://www.cs.princeton.edu/software/index.html A new machine definition file will need to be generated for each profile in order to use the compiler.

4. C compiler (cont.) The input the the C compiler is standard ANSI C code. The output is an assembly program written in the defined instruction set architecture.

5. Assembler An assembler is available for the DLX processor using TI’s retargetable Meta Assembler TIM. The url for the basic TIM files is http://users.ece.gatech.edu/~hamblen/TIM The url for a windows version of TIM is http://users.ece.gatech.edu/~hamblen/book/wintim /index.html. I have not used the windows version of this tool, but it may be easier to use so I’m checking it out.

6. Assembler (cont.) A new TIM definition file will need to generated for each instruction set architecture. The input to the TIM assembler is an assembly program. The output is machine code. By machine code I mean the bit stream that the decode stage is designed to decode.

7. tim2vhdl This is a tool to convert the machine code that is generated by TIM to VHDL code that can be incorporated into the fetch.vhd module. A full explanation of tim2vhdl, including source code, can be found on pages 14-17 of the report-4500.ps file posted to egroups.

8. timtool The assembly file that is generated by the lcc compiler is not precisely compatible with the input needs of TIM. This scripts corrects those problems. The input is the assembly program generated by lcc. The output is the assembly program that is fed into TIM.

9. timtool (cont.) timtool is responsible for several formatting changes as well as adding/changing some of the code generated. A full explanation of timtool, including source code, can be found on pages 59-65 of the report-4510.ps file posted on egroups.

10. Overview of DLX architecture

11. Reusable modules Modules that should be reusable with little or no modification are the clock, multiply, adder, divider, and multiplexer. The is also a considerable amount of code that can be partially reused or used as an example. The execute and decode unit are good examples of this.

12. DLX Instruction Flow

13. Profile Instruction Flow