1. D. M. Lee, LANL 1 07/10/07 Forward Vertex Detector Status: R&D: Scientific and Technical Resources Technical Design Overview Design status R&D Cost and schedule Scientific Resources and Manpower Issues and Concerns

2. D. M. Lee, LANL 2 07/10/07 Forward Vertex Detector Technical Design – Specifications Cover the Muon Spectrometer Acceptance – both Arms (10-35 deg) Full Azimuthal coverage – hermetic DCA resolution < 200 µ m at 5 GeV ≥ 3 space points / track Maximum Radiation Length < 2.4% Survive 10 year integrated dose = 200k Rad Low Occupancy in Au – Au Central < 10.0% Co-exist with barrel VTX Compatible with PHENIX DAQ

3. D. M. Lee, LANL 3 07/10/07 Forward Vertex Detector Technical Design – Mechanical Combined VTX + FVTX without outer enclosure FVTX “Big Wheel” Location for all readout electronics

4. D. M. Lee, LANL 4 07/10/07 Forward Vertex Detector Technical Design – Mechanical 4 hermetic disks, z=18.5 – 38 cm 48 wedge segments per disk ( 7.5 deg) Inner disk radius = 3.5 cm (4.5 cm active) Outer disk radius = 17 cm 75 micron strips, 550,000 strips/endcap Total power load of disks = 50 W each Power load of Readout cards= 450 W in big wheel Room temperature operation Each Endcap

5. D. M. Lee, LANL 5 07/10/07 Forward Vertex Detector Technical Design – Mechanical Mechanical Integration with the Barrel VTX Fully integrated model

6. D. M. Lee, LANL 6 07/10/07 Forward Vertex Detector Technical Design – Wedge Backplane (0.76mm graphite fiber composite) Screw (nylon) Pin hole (for alignment) Pin hole (for alignment) HDI Connectors for extension cables Detector FPIX Chips (26, 13 ea. side) Screw (nylon) All bonded with rigid epoxies HDI Detector FPHX Chips Backplane Rigid, thermally conductive epoxy Rigid epoxy

7. D. M. Lee, LANL 7 07/10/07 SensorHDI FPHX Chips (13 per column) Mini-strips are oriented to approximate an arc Forward Vertex Detector FVTX Sensor Sensor – 2 columns of strips – 1664 strips per column – strip length 2.8 to 11.2 mm – 75 µ m spacing – 48 wedges per disk (7.5˚/sensor, ~15˚/wedge) – 0.5 mm overlap with adjacent wedges FPHX Chip – 1 column readout – 128 channels – ~ 70 µ m channel spacing – Dimensions –9mm x 1.2 mm

8. D. M. Lee, LANL 8 07/10/07 Sensor layout R&D prototyping design Zoom in … one FPHX chip testing pads (both staged) bonding pads Guard ring Dicing edge Vaclav Vrba, Prague Thickness 300 µm Doping of starting materialn type Resistivity2-5 K  -cm Wafer diameter6 “ preferred PassivationSiO or SiN

9. D. M. Lee, LANL 9 07/10/07 Sensor R&D A real prototype Vaclav Vrba, Prague

10. D. M. Lee, LANL 10 07/10/07 HDI Stack Up GND Signal Power HDI trace count 2 R/O lines x LVDS pair x 26 chips 104 4 Download and Reset lines 4 2 Clocks x LVDS pair 4 1 Calibration line 1 113 Forward Vertex Detector HDI-High Density Interconnect High Density Interconnect (HDI) – kapton flat cable to transfer data from the chip to the read- out electronics – 176 μm thick – 4 copper planes (ground, power, 2ea signal), 5 Kapton films, 8 glue layers HDI glue kapton

11. D. M. Lee, LANL 11 07/10/07 Max deflection 10.4μm Zero deflection (boundary conditions) Wedge R&D Analysis Temperature & Stress 3-D Temperature Contour Max Tº = 20.3ºC Warmest ROC Min Tº = 15ºC Warmest FPHX Chip is 5.3ºC Warmer than Back Edge of Backplane 3-D Distortion Contour

12. D. M. Lee, LANL 12 07/10/07 Forward Vertex Detector Half-Disk Assembly: Details Thermally conductive Silicone Plastic inserts for screws and pins Single piece plastic insert for screws and pins Standoff plate Foam core Honeycomb core

13. D. M. Lee, LANL 13 07/10/07 Disk-Level R&D Modeling Thermal distortion Max deflection of detector ~8μm Fundamental vibration mode: 164 HzDistortion due to cooling

14. D. M. Lee, LANL 14 07/10/07 Half Cage Assembly Cooling hose (silicone) Station 1Station 2Station 3Station 4 Z Y Al Honeycomb core, C face sheets

15. D. M. Lee, LANL 15 07/10/07 Liquid Cooling Circuit R&D FVTX Inlet: 10°C, ~5 psig station 4: ~20.6°C Outlet plane 4: 10.3°C FVTX Outlet: 11.1°C, ~3 psig station 3: ~20.9°C station 2: ~21.2°C Outlet plane 3: 10.6°C Outlet plane 2: 10.9°C Warmest Chip, station 1: ~21.4°C

16. D. M. Lee, LANL 16 07/10/07 Half Cage Assembly R&D Gravity Sag (Max = 3.2µm) Drum mode shape (f=137.7 Hz)

17. D. M. Lee, LANL 17 07/10/07 VTX+FVTX Finite Element Model R&D First Mode: 38Hz

18. D. M. Lee, LANL 18 07/10/07 FPHX Chip Design R&D Phase 1 Designed by FNAL Based upon well tested FPIX2 chip design Data push readout over 2 output lines Zero suppression with programmable threshold Fully programmable logic with masking capabilities Data contains: – 3 bit ADC – 7 bit Strip Information – 6 bit Beam Counter Noise 150e + 140e/pf Power <110 µW per channel Data Word structure TBD Time (ns)

19. D. M. Lee, LANL 19 07/10/07 FPHX Chip Design Specifications – Phase 2 Match to 75 µm strip spacing, ~ 70 µm channel spacing Design to strip capacitance ≤ 1.5 pf Dynamic range to extend to 50000 e - Noise ≤ 425 e - Chip readout, 4 hits in 4 beam clocks Use Data push architecture 4 bit ADC required, 5 bit goal, with programmable reference voltages 2 output lines All other FPIX2 specifications* * FPIX2 has same output architecture as FPHX so FPIX2 is used for testing DAQ designs

20. D. M. Lee, LANL 20 07/10/07 Forward Vertex Detector Technical Design – Electronics DAQ Readout electronics split into two parts – Near the detector (ROC) – Compresses and serializes the data from a group of chips – Radiation tolerance  use FLASH based FPGAs from Actel – Fiber link to the control room – In the Control Room (FEM) – Buffer data for 64 beam clocks – Send data to DCM upon LVL1 trigger request – SRAM based FPGAs from Xilinx N FPHX Chips ROC FEM PHENIX DCM 1,2 output lines per chip Stream of 20-bit data words @ 150 MHz– under design Zero suppression Programmable Threshold Buffers Data for 64 Clocks Upon Lvl-1 grab relevant data Build packet Send data to DCM/LVL1 Pass Clock to ROC Slow controls manager PHENIX Standard Limit <2000 20-bit words/DCM GTMLVL1 fiber Slow Control Deserialize and Combine data from several FPHX chips Strip Synch Words Send data over fiber Calibration 2.5 Gb/s fiber link Inside IRIn Counting House

21. D. M. Lee, LANL 21 07/10/07 ROC Design Specifications Combine serial data from 52 FPHX chips ( 2 wedges)  Synchronize readout and strip off Sync Words  Generate ~130 MHz Serializer Clock  Provides Control, Download and Calibration signals for the chips  Append CHIP ID to the data  Send parallel data word output at 130 MHz over 2 fiber interface to the FEM Move from ACTEL A3PE600 to ACTEL A3PE3000 FLASH based FPGA  = done

22. D. M. Lee, LANL 22 07/10/07 ROC Block Diagram

23. D. M. Lee, LANL 23 07/10/07 ROC Prototype R&D USB Interface Actel Board DigiIO 8-chip module Actel A3PE600 prototype board Slow control via USB interface (DLP-2232M) Output data via NI-6534 PCI card at 20 MHz (up to 640 Mbps) Test an 8-chip FPIX module (FPIX is progenitor of FPHX chip and has similar digital backend)

24. D. M. Lee, LANL 24 07/10/07 ROC Prototype R&D USB Interface Actel Board DigiIO 8-chip module Covers 30 deg (16 wedges)

25. D. M. Lee, LANL 25 07/10/07 FEM Design Specifications FEM receives data from a single ROC channel over two fibers at fixed rate of 2.5 Gbits/s Main functionality – Store the data by BCO counter  – Buffer data for 64 BCO clocks  – Read the data from certain clock to output buffer at 300 MHz  – Send the output buffer content to the DCM  Plan to combine the data from 4 FEM channels on single FEM board Implementation – Xilinx mid-scale Virtex-4 FPGA VC4VSX35 – Use built-in FIFOs and Relationally Placed Macros (RPMs) for maximum performance and predictability (Provided by XILINX)  = done

26. D. M. Lee, LANL 26 07/10/07 FEM R&D Design tested with single chip readout and “fake” data and running chip calibration chain 100% of hits propagates through FEM with realistic triggered readout Readout to PC tested at 640 Mb/s rate using NI-6534 readout board Virtex-4 test board FPIX Chip

27. D. M. Lee, LANL 27 07/10/07 Test of Calibration System Test each pixel by injecting 64 pulses at gradually increasing amplitude Upper figure shows histogram of turn-on curve for one channel Lower figure shows noise Inject capacitor = 3fF  Noise ~ 102 e

28. D. M. Lee, LANL 28 07/10/07 Summary Designs and R&D Mechanical design is well along and mature Some mechanical prototyping needed Sensor prototype finished and ready for testing Readout ROC and FEM prototyped and tested – Fiber link prototyped and under test – All other requirements met – Calibration circuit designed and to be implemented on ROC board FPHX conceptual design done, first pass FPHX R&D critical path FEM with fiber readout

29. D. M. Lee, LANL 29 07/10/07 Remaining R&D DAQ – ROC and FEM electronics PC boards are now in progress and will be complete by Jan 2008 – LDRD funded FPHX – complete design and chip layout – SOW in progress, signed by LANL and FNAL, ready for BNL signature – Start July 2007 FPHX – First MOSIS run, early 2008 Mechanics – some prototyping desirable 2007 FEM with fiber readout

30. D. M. Lee, LANL 30 07/10/07 Mechanical structures – HYTEC estimate based on prior experience with VTX and ATLAS Sensors – Quotes from CIS, MICRON FPHX – FNAL estimate based on prior experience Electronics Interface DAQ – estimate based on prior experience Wire bonding – PROMEX quote DCM,slow controls, etc – Muon system experience, Steve Boose Cost Basis - Major Items

31. D. M. Lee, LANL 31 07/10/07 FVTX Schedule Assumptions Construction start – January 1, 2008 ( 2 nd QTR FY08) LANL R&D start - January 2006 BNL R&D start – October 2006 Schedule durations determined by engineering estimates, vendor quotes Duration of project made to match funding profile VTX and LDRD impact the schedule especially R&D Wedge assemblies tested at a rate of 3/day ( automated computer tests) Disk assembly assembled in 2 week, metrology of disk in 2 week Commissioning for 8 months

32. D. M. Lee, LANL 32 07/10/07 FVTX Major Cost Items Major ItemBase CostContingencySum Mechanical Ladder and support $416k 26%$524k Sensor $410k 26%$517k FPHX Chip $240k 36%$326k Wire bonding $188k 26%$237k ROC boards $443k 36%$603k FEM boards $323k 36%$440k HDI $111k 25%$139k Total Project (FY07) $3669k 25%$4595k

33. D. M. Lee, LANL 33 07/10/07 Scientific resources and Manpower

34. D. M. Lee, LANL 34 07/10/07 Scientific resources and Manpower InstitutionConstruction ResponsibilitiesPost Construction Responsibilities BARC, Mumbai, IndiaSimulationsData Analysis Brookhaven National Laboratory (BNL physics, C-AD) FVTX detector integration into PHENIX, E.S.H&Q, commissioning Data Analysis CEA, FranceOfflineData Analysis, Software Charles University, Prague, Czech RepublicSensor, SoftwareData Analysis Czech Technical University, Prague, Czech RepublicSensor, SoftwareData Analysis Columbia UniversityWedge and sensor QA, FPHX, commissioningData Analysis, Calibrations, Software High Energy Accelerator Research Organization (KEK), Tsukuba, Japan TBDData Analysis Iowa State UniversityLVL-1Data Analysis Institute of Physics, Academy of Science, Prague (Czech)Sensor, softwareData Analysis, Software Kyoto University, Kyoto 606, JapanTBDData Analysis, Software Los Alamos National LaboratoryProject Management DAQ electronics, FPHX, commissioning Mechanical system Oversight of the mechanical system Data Analysis, Calibrations, Software New Mexico State UniversitySimulation study, wedge, disk, cage assembly,commissioningData Analysis, Calibrations, Software University of Jyvaskyla, FinlandTBDData Analysis, Software University of New MexicoHDI, flex cabling, Sensor Q/A and testing, commissioningData Analysis, Calibrations, Software Yonsei University, Seoul, KoreaTBDData Analysis, Software 7-2-2007 Draft

35. D. M. Lee, LANL 35 07/10/07 Infrastructure and Facilities Columbia – Electronics lab and test equipment, 400 sq ft clean room Czech – Electronics lab and test equipment, clean room LANL – Electronics lab and test equipment, 600 sq ft clean room UNM – 256 sq ft clean room, probe station, test equipment BNL – lab space, measurement facilities LANL Clean Room UNM Clean RoomColumbia Clean Room

36. D. M. Lee, LANL 36 07/10/07 Issues and Concerns FPHX is new and the highest risk item – will require careful attention Integration – VTX/FVTX integration – Strip layers still being designed – Big wheel electronics Electrical – grounding and shielding Extensive system tests will be required

37. D. M. Lee, LANL 37 07/10/07 Backups

38. D. M. Lee, LANL 38 07/10/07 Schedule

39. D. M. Lee, LANL 39 07/10/07 Schedule

40. D. M. Lee, LANL 40 07/10/07 Schedule

41. D. M. Lee, LANL 41 07/10/07 Schedule

42. D. M. Lee, LANL 42 07/10/07 Cost

43. D. M. Lee, LANL 43 07/10/07 LANL LDRD-DR - $589.9k expected ( to date) finish DAQ Interface Modules - $489.9k ($100.9k) Jan2008 Mechanical design - $100k ($100k) Apr2007 LANL Heavy Ion Program - $130k Mechanical design - $130k ($130k) Apr2007 BNL R&D funds - $345k FPHX design and Prototype - $295k ( $67k) Jul2008 Mechanical prototype - $50k ($0k) Jan2008 Czech Institute of Physics, Academy of Sciences Sensor – prototype finished – contribution R&D Costs Associated for FVTX

44. D. M. Lee, LANL 44 07/10/07 Disk Detail

45. D. M. Lee, LANL 45 07/10/07 VTX – FVTX Integration The need began 2 years ago But we found this 2 months ago Interference!

46. D. M. Lee, LANL 46 07/10/07 Funding Profile

47. D. M. Lee, LANL 47 07/10/07 Manpower Fraction 65% 35%