1. Data Word Length Reduction for Low- Power DSP Software Kyungtae Han March 24, 2004

2. Low-Power Software Portable computing demands minimizing power dissipation due to limited power Minimizing power consumption  Reduce supply voltage  Decrease switching activity Software can reduce power consumption  Ordering of operation  Changing of number representation  Reducing of data word length

3. Objectives and Problems Objectives  Power analysis of multipliers for variable word length for low-power software  Software level power minimization with reducing data word length while keeping hardware structure Problems  How to analyze and measure power consumption for low- power software  How much can shorter data word length reduce power consumption?

4. Power Analysis of Embedded Software [Tiwari, Malik, and Wolfe, 1994]  Measuring power of instruction sets  Formulated an instruction level power model [Lee, Tiwari, Malik, and Fujita, 1997]  Found multiplier in the multiply and accumulate (MAC) unit is usually a major source of power consumption in typical DSP applications  Observed the wide current variation of MAC instructions according to the two values being multiplied in MAC unit

5. Word Length for Low Power [Chandrakasan et.al, 1995]  Showed that the word length affects all key parameters of a design, including speed, area, and power  Switching activity is used for power estimation [Erdogan and Arslan, 1996]  Demonstrated power reduction with different coefficient word lengths in a modified DSP processor  Used data bus and coefficient bus for multiplication

6. Preliminary Results Array multiplier with SDF  16-bit array multiplier  Different data word lengths  10,000 random data  Node transitions counted Transition counts Input dataMaxMinStdMean 16 bits31523833191863 8 bits11980163518 4 bits30505494

7. Summary of Talk and Plans Summary  Power analysis of embedded software  Word length for low power  Short data word length reduces power consumption Plans  Formulate power model for different input word lengths being multiplied  Find tradeoff with power consumption and precision  Different architecture: Booth Radix-4, Wallace multipliers  Apply for digital FIR filter implementation using SDF domain

8. Backup Side: Software Level Power Power consumption