1. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Multichannel Time-Variant Readout Electronics of DePMOS based APS for the XEUS Wide Field Imager M. Porro, S. Herrmann, L. Strueder, J. Treis P. Lechner G. Lutz, R. H. Richter C. Fiorini, L. Bombelli, G. Langfelder, A. Longoni W. Buttler MPI for extraterrestrial physics PNSensor GmbH MPI for physics Politecnico di Milano & INFN Ingenieurbuero Werner Buttler

2. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia XEUS project (X-ray Evolving Universe Spectroscopy) Exploring the early universe by imaging spectroscopy in the X-ray band (100 eV – 30 keV) Observation of the hot Universe at high redshifts Device active area 7.68 x 7.68 cm 2 Device thickness 450  m Pixel size: 75 x 75  m 2 Position resolution ca. 30  m Total 1024 x 1024 pixel cells Energy resolution @ Mn-K  125 eV Energy resolution @ C-K  50 eV System noise 3-5 e - ENC

3. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia XEUS WFI specifications XMM EPICXEUS WFI energy range0.1... 15 keV0.1... 20 keV focal length7.5 m50 m angular resolution15 arcsec2 arcsec focal plane res.36 µm / arcsec250 µm / arcsec field of view30 arcmin5 arcmin collection area 1 keV0.5 m²6 m² (30 m²) time resolution70 msec1... 5 msec operating temp.130 K> 180 K thickness 300 µm ➞ 500 µm pixel size150 µm ➞ 75 µm detector area6 x 6 cm² ➞ 7.68 x 7.68 cm² format400 x 400 ➞ 1024 x 1024 readout speed leakage current Active Pixel Sensor» 1 preamp / pixel » random accessible pixels » no charge transfer Specifications

4. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia The DePMOS Concept p-channel MOSFET integrated on high-ohmic, sideward depleted n-substrate a potential minimum is formed by S/D potentials aided by a deep n implantation electrons are collected in an internal gate close to the surface the transistor current is modulated by charge collected in the internal gate the transistor can be switched on/off by an external (top) gate An n+ clear contact surrounded by a clear gate is used to remove the charge from the internal gate

5. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia DePMOS Properties DePMOS provides detection and amplification jointly DePMOS is free of interconnection capacitances The internal gate exists regardless of a current flowing in the DePMOS channel or not. Power consuption is minimized Multiple non-desctructive readout is possible matrix pixel 75 x 75 µm² DEPFET geometryW = 47 µm L= 5 µm dedicated technology 2 polysilicon layers 2 metal layers leakage current level 100 pA/cm² 16 fA/pixel

6. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia APS – matrix organisation global contacts for drain (source), back contact, substrate, … 1 active row DEPFETs ON » readout & reset all other pixels DEPFETs OFF » integration random accessible pixels » window mode, mixed mode sources connected column- wise gate, clear & cleargate connected row-wise

7. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia APS for the WFI 1024 x 1024 pixel 7.68 x 7.68 cm² 5 arcmin FOV full frame mode readout time:~ µsec / row ~ msec / frame window mode mixed mode fast timing mode e.g.16 x 16 pixel ~ 100.000 cps »fast transients of bright point sources  APS readout modes

8. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia CAMEX 64 G / K 64 channel low noise voltage amplifier 64 channel 8-fold CDS filter 64/1 analog multiplexer source follower gain 3.7 µV/el. Switcher II 64 channel control chip 2 ports / channel integrated sequencer high voltage CMOS process (> 20 V p-p) 50 MHz clock DEPFET APS – prototypes for the XEUS WFI

9. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia incomplete clear! DEPFET – signal measurement (time variant readout) measure signal levels 1. before clear -» signal 2.after clear-» baseline 3.calculate difference

10. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia DePMOS Linearity The drain current is measured Laser intensity is calibrated with an X- ray source Variation of the total charge by increasing number of the laser pulses per cycle time clear pulses laser pulses output measurements drain current Integral non-linearity <0.4% input range of 200 keV

11. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Front end Configurations and Equivalent Input Capacitance source follower readout drain current readout Charge/Voltage Gain 4-6  V/el. Charge/current gain (g Q ) 200-350pA/el. The signal and the noise sources are referred to the external gate Definition of Equivalent Input Capacitance C EQ Q IN in the internal gate ->  V S or  I D  V EG external gain signal that produces the same  V S or  I D C EQ =Q IN /  EG Q IN VSVS IDID  V EG C EQ =Q IN /  EG Measured C EQ =35-40fF gm=50  S I D =60  A

12. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Noise Spectral Density I D 60  A gm 50  S √a f =3  V √a=18nV/ √Hz √(8/3)kT/gm= =14nV/ √Hz noise corner 30kHz

13. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Readout Requirements electronics requirements: multichannel ASIC time-variant readout variable readout speed maximum readout speed 4  S total ENC <4 el. r.m.s. dynamic input range: 40keV Linearity <1% DePMOS parameters C EQ =40fF gm=50  S g Q =200pA/el. V/c=4  V/el. √a=14nV/ √Hz √af=3  V

14. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia ASIC Development CAMEX Chip In collaboration with Mr. W. Buttler IMS 0.8  m CMOS 5V 8-fold Multi-correlated Double Sampling Source Follower readout First Prototypes already tested -64 channels -no adjustable bandwidth 128 channel version with adjustable bandwidth under design VELA Chip In collaboration with Politecnico di Milano and INFN (Vlsi ELecrtonics for Astronomy) AMS 0.35  m CMOS 3.3V Trapezoidal Weighting Function with Switched Current Technique Source Follower readout Drain Current readout First submission June 2006 First prototypes in September 2006

15. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia MCDS-CAMEX CAMEX 64 G / K ac-coupled, low noise voltage amplifier 64 channel parallel 8-fold CDS internal PMOS current load integrated CDS sequencer 64/1 analog output serializer power consumption ≤ 0.6 W row processing time ≥ 4 µsec 128 channel version in design

16. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Energy resolution of the matrix shaper parameters: A1/t=1.26x10 6 A 2 =1.27 cycle time: 16  s Predicted ENC: 3.4 el. r.m.s. C eq =40fF Measured ENC on noise peak: 3.6 el. r.m.s. with single pixel hits spectrum 133 eV @ 5.9 keV, T = -40 °C

17. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia MCDS Filtering optimization A1/tA2 Cycle time [  s] Predicted ENCMeasured ENC 1.26x10 6 1.27163.43.6 1.26x10 6 1.2743.4 0.32x10 6 1.16162.1 The used WF has quite high slope The bandwidth is not optimized for the used speed Optimizing the bandwidth an ENC of 2.1 el. is predicted With the used bandwidth it should be possible to read-out the pixel in 4  s The bandwidth must be adjusted for every speed setting A scalable trapezoidal WF would provide the near optimum filter for Series noise at every speed setting

18. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Trapezoidal WF with SCT subtraction out time Vout time Vout 1° integration 2° integration Current proportional to the input charge deposited into the DePMOS Double integration of this current Subtraction of the output of the two integrating stages after the first integration The output is maximized when the input signal arrives between the two integration phases (Flat- top region) time Vout subtraction current proportional to the charge stored into the pixel

19. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Practical Implementation 1 2 3 1 2 3 the charge integrated in the first integration is transferred to a second stage (subtraction stage) the first stage is resetted before the second integration at the end of the second integration the output of the second stage gives the difference between the two integrated values out integrator stage subtraction stage

20. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia MCDS vs SCT MCDS Benefits: The gain is almost independent on the timing An offset of the input signal is not critical Drawbacks: The equivalent bandwidth depends on the timing (An adjustable low- pass filter is needed) A real finite width WF is not feasible Higher switching noise SCT Benefits: The equivalent bandwidth is independent from timing A finite width filter function is feasible Lower switching noise Drawbacks: An offset of the input signal is critical and can heavily deteriorate the dynamic range The gain depends on the timing (an adjustable gain is needed)

21. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Source Follower vs. Current readout Benefits: The input signal is AC coupled. It is relatively easy to cope with: - non homogeneity of the DePMOS matrix - eventual Vth shifts Drawbacks: The speed of the system is limited by the gm of the DePMOS and by the Capacitance of a matrix Source Line (30-40pF) The voltage step at the source must be converted into a current (more suitable for MCDS) Only a small signal amplification is possible because of the limited dynamic range Benefits: The DePMOS drain current is directly used as the input signal of the integrator (pixel gain 200-300 pA/el) all DePMOS terminals are at a fixed potential The speed is no more limited by the Source line capacitance Drawbacks: It is more complex to cope with the non homogeneity of the Matrix. A current cancellation circuit is needed for each individual pixel Source Follower Current Readout V2I gate drain Bias current source gate drain source Bias current subtraction

22. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Source Follower: V2I C R V2I CFCF C IN dominant pole MB second pole 0V I OUT Vin The output current is not set by a feedback: mismatch can be important Output current must be in the range of few mA to limit the size of the capacitances of the integration stage Converted current in injected into the output mirror by a drain (MB drain) The second pole of the loop gain is given by C F and 1/gm MB. The stability is independent from R V2I that can be high (tens of k  ). M 1

23. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia V2I Noise analysis R V2I CFCF C IN 4kT/R S (8/3)kTgm M 1 e n,AMP i n, MIR 4kT/R V2I R S >1/gm DePMOS =20K -> R S >100K e n,AMP at the input. gm AMP 10mS W/L 800/.5 R V2I attenuated by (C F /C IN ) 2 =100 R V2I =16K i n,MIR =(2/3)KTgm MIR multiplied by (R V2I M) 2 dominant noise source

24. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia S.F. Noise spectral density Elecronics e N =3e-17 V^2/Hz (5.5 nV/  Hz) a f =1.7e-13 V^2 DePMOS e N =3e-16 V^2/Hz (17 nV/  Hz) e N =2e-16 V^2/Hz (14 nV/  Hz) [gm=50uS] a f =9e-12 V^2

25. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia S.F. Simulations Simulated weighting functions voltage step applied to the input of the V2I DePMOS rise-time is not considered Input dynamic range: 0-40mV equivalent to 0-10000 el. with S.F. DePMOS Output Range: 0-1.6 V total width: 4  s, 8  s, 16  s non linearity <0.4%

26. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia S.F. ENC Flat-top 500ns DePMOS theoretical noise gm DePMOS 50  S CS resistor 100K DePMOS rise-time not considered

27. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Line capacitance The Capacitance of one matrix column: mainly given by the crossing of metal lines crossing 10x10 mm 2 C OX =5.5 fF 4 crossing/pixel 500pixel/column Crossing with Silicon and polysilicon C GS and C CD give a minor contribution column capacitance for the final APS 30-40pF

28. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia S.F. Rise Time RISE TIME: V2I: 15ns DePMOS+V2I: 700ns R V2I 30pF 10-90% 15ns 10-90% 700ns gm 100  S r O =150K

29. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia S.F. WF distortion integration time: 1.5  s flat top:.5  s total width: 4  s integration time: 6  s flat top:2  s total width: 14  s

30. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Drain Current readout Bias current cancellation Integrator Stage Subtraction stage The DePMOS Drain signal current is sent directly to the integrator. An individual bias current cancellation circuit is needed

31. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Current Readout: Current storage electron signal in the internal gate I BIAS +I S +n(t) VHVH The integrator is disconnected The DePMOS current (bias+signal) is stored in a memory cell At the end of this phase an unavoidable mismatch n O exists due to: 1) sampled noise when the switch opens 2) finite gain of the amplifier V H +n H I BIAS +I S +n O

32. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Current Readout: double integration I BIAS +I S +n(t) V H +n H I BIAS +I S +n O n(t)-n O electron signal in the internal gate 1° integration: The noise n(t) + offset n O is integrated pixel is cleared 2° integration: the noise n(t) + offest + signal I S is integrated from the subtraction of the two integrated quantities the offset n O is cancelled internal gate empty n(t)-n O -I S

33. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Weighting Function 4us Trapezoidal weighting functions low-pass at 25MHhz width 3.5us

34. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia ENC evaluations: noise sources ConditionsENC DepMosENC RsENC CASENC AMP1ENC AMP2ENC velaENC totENC add NOMINAL3.261.652.100.720.792.884.351.09 gm = 50uS C stray = 30pF Rs = 100Kohm gain = 200pA/el Weighting functions width = 3.5us

35. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Conclusion DePMOS characteristics match the requirements of XEUS Mission A First Multi Channel MCDS Readout ASIC has already been tested with a 64x64 APS prototype. Obtained results are in agreement with theoretical predictions: -3.6 el. r.m.s. measured -line readout speed of 16  s To overcome the limitations of the available electronics two new circuits are under development -Trapezoidal Weighting Function ●Source Follower ●Drain Readout From simulations the most promising solution for fast timing is the current readout mode: -Line readout speed 4  s -around 4 el. r.m.s. To further improve the performance of the system two ways are possible: -increase the gain of the pixel (gm and gq) -increase the number of readout channel ( time available for each measurement)

36. Matteo Porro MPI Halbleiterlabor map@hll.mpg.de FEE 2006 Perugia Radiation Hardness (Laci ANDRICEK MPI HLL)