1. Manas Bajaj 1, Russell Peak 1, Dirk Zwemer 2, Thomas Thurman 3, Michael Dickerson 4, Kevin Brady 5, John Messina 5 1. Georgia Institute of Technology 2. AkroMetrix, LLC 3. Rockwell Collins, Inc. 4. InterCAX, LLC 5. National Institute of Standards and Technology Next Generation Simulation-based Design Technologies for Electronics Product Realization AkroMetrix PDE 2005 The 7th NASA-ESA Workshop on Product Data Exchange (PDE) April 19-22, 2005 Manufacturing Research Center, Georgia Tech, Atlanta

2. 2 © Copyright 2005 Abstract Next Generation Simulation-based Design Technologies for Electronics Product Realization The realm of electronics product realization is marked by an extremely fast-paced market, stringent demands for product reliability and high importance to innovative design. Further, the time-to-market and the cost-to-realize play a critical role for product success. However, these attributes pose conflicting constraints on the realization process. While engineers need to converge quickly on a set of design alternatives, the high demand for reliability increases the breadth of behavioral simulations across the design space. Further, the multi-disciplinary nature poses integration challenges due to a disparate set of engineering tools, model representations, and simulation techniques. In this presentation, we shall focus on the following three technical areas to alleviate these hurdles in knowledge management during electronics product realization: (1) Design-Analysis Integration: In order to quickly converge on a set of feasible design alternatives while covering a wide range of behavioral simulations across the design space, it is essential for engineers to synthesize analysis and solution-specific product models for a given design alternative. This process is guided by ascertaining the context of analysis, identifying possible idealizations and mapping information from design specifications to the analysis specifications. Further, the modularity of this process is essential to explore all possible alternatives. We leverage from over a decade’s worth of experience spanning methodologies and tools (www.eislab.gatech.edu/research/dai/) and some recent advances in this area to demonstrate current and envisioned technologies for seamless design-analysis integration.www.eislab.gatech.edu/research/dai/ (2) Standards-based Knowledge Representation: In order to create high-fidelity design, analysis and manufacturable product models, it is essential to use a detailed and standard ontology for electronics product data specification. In this light, we employ STEP AP 210 (www.ap210.org) for electronic assembly packaging and design as the underlying representational structure for creating and archiving product models. Further, we use a harmonized set of STEP- based schemas for product model specifications across the design-analysis integration bridge. In this presentation, we shall focus on the ability of a standards- based knowledge representation scheme to support product and process related knowledge for electronics PLM.www.ap210.org (3) Experimental Validation of Simulation Techniques: In general, a simulation-based methodology needs to be validated against experimental results to justify reuse and instill confidence in decisions based on simulation results. In this presentation, we shall also demonstrate on algorithmic techniques for validating simulation results with experimental data and discuss some critical issues concerning the same. Further, in this presentation, we will exemplify recent developments in the three technical areas using thermo-mechanical warpage analysis problem for printed circuit boards and assemblies, as part of the current collaborative effort between co-author organizations. http://eislab.gatech.edu/pubs/seminars-etc/2005-cpda-dsfw-peak/ This document may identify commercial product names and materials to describe certain procedures or to provide concrete examples (i.e., to help clarify abstract concepts via specific instances). In no case does product or material identification imply recommendation or endorsement by the authors or their organizations, nor does it imply that such items are necessarily the best available for the purpose. Company, product, or service names may be included that are trademarks or service marks of others.

3. 3 © Copyright 2005 Contents u Role of Simulation-based Design in Electronics Product Realization Theme -- Warpage Worthiness u Enabling Technologies –Design-Analysis Integration –Standards-based Product and Process Models –Computer-based engineering framework for analysis, validation and design enrichment u Future Research

4. 4 © Copyright 2005 Electronics Product Realization Environmental Placement FabricateTest/Inspect Part Symbol & Footprint Assemble Doc/Proc/Reg Guidelines Corrections Release Learn today Utilize tomorrow Functional Layout Requirements RoutingReview Design Build

5. 5 © Copyright 2005 Simulation-based Design Electronic Packaging Examples: PWA-B Analysis Modules (CBAMs) of Diverse Mode & Fidelity Design Tools Laminates DB FEA Ansys General Math Mathematica Analyzable Product Model XaiTools PWA-B XaiTools PWA-B Solder Joint Deformation* PTH Deformation & Fatigue** 1D, 2D 1D, 2D, 3D Modular, Reusable Template Libraries ECAD Tools Mentor Graphics, Accel* Analysis Tools PWB Warpage 1D, 2D Materials DB PWB Layup Tool XaiTools PWA-B STEP AP210, GenCAM**, PDIF* * = Item not yet available in toolkit (all others have working examples) ** = Item available via U-Engineer.com DFX

6. 6 © Copyright 2005 Theme Assessing Thermo-Mechanical Warpage of PWBs u Definition: WARPAGE is out of plane deformation of the artifact, caused by differential (non-homogenous) shrinkage or expansion of elements composing the artifact. Out of plane deformation of a linear element  = (  b L 2  T) / t where L: Undeformed Length; t: Undeformed Thickness;  T: Temperature Change;  b : Specific Co-efficient of Thermal Bending Saddle Deformation Bowl Deformation Warpage of 2D artifacts ( basic modes)

7. 7 © Copyright 2005 Warpage – Impact and Requirements Ref: Thinking Globally, Measuring Locally Editorial by Patrick Hassell, AkroMetrix Impact u Low manufacturing yield and high rework of interconnects –Lack of co-planarity of component footprints –Fine pitch technology –Low solder paste volume Requirements u Managing warpage requirements –Enforce local warpage requirements –Relax global warpage requirements

8. 8 © Copyright 2005 Multi-Representation Architecture (MRA) for Design Analysis Integration Tree View Bare PWB ElectricalMechanicalManufacturability WarpagePTH Fatigue Layered Shell Effective Materials Properties Finite Element Manufacturing Product Model Analysis Product Model Context-Based Analysis Model Analysis Building Blocks Solution Method Model

9. 9 © Copyright 2005 Multi-Representation Architecture (MRA) for Design Analysis Integration Stepping-Stone Model View Solution Method Model  ABBSMM Analysis Building Block Context-Based Analysis Model SMMABB  APMABB CBAM APM Manufacturing Product Model (STEP AP210-based) Solution Tools (ANSYS, …) Printed Wiring Assembly (PWA) Solder Joint Component PWB body 3 2 1 4 T 0 Printed Wiring Board (PWB) Solder Joint Component Analyzable Product Model

10. 10 © Copyright 2005 Complex Features Affecting Thermo-Mechanical Behavior PCB outline Comprised of straight lines and arcs (primitive level) Mechanical (Tooling / Drilling) Hole Circuit Traces land plated through hole via Footprint occurrence This comprises of four lands, in this case. The component sits atop the lands. Complete trace curve not shown M150P2P11184 M150P1P21184

11. 11 © Copyright 2005 Example PCA design: Hexapod (from EAGLE displayed in STEP-Book AP210)

12. 12 © Copyright 2005 Product Enclosure External Interfaces Printed Circuit Assemblies (PCAs/PWAs) Die/ChipPackage Packaged Part Interconnect Assembly Printed Circuit Substrate (PCBs/PWBs) Die/Chip STEP AP210 (ISO 10303-210) Domain: Electronics Design R ~950 standardized concepts (many applicable to other domains) Development investment: O(100 man-years) over ~10 years 2003-04 - Adapted from 2002-04 version by Tom Thurman, Rockwell-Collins Configuration Controlled Design of Electronic Assemblies, their Interconnection and Packaging

13. 13 © Copyright 2005 Use of STEP AP210 (ontology) for MPM / APM description Standard for Electronic Assembly Interconnect and Packaging Design Assembly Models User View Design View Component Placement Material product Complex Assemblies with Multiple Interconnect Component / Part Models Analysis Support Package Material Product Properties “White Box”/ “Black Box” Test Bench Requirements Models Design Constraints Interface Allocation Functional Models Functional Unit Interface Declaration Network Listing Simulation Models Signals Test Bench Interconnect Models User View Design View Bare Board Design Layout templates Layers Configuration Mgmt Identification Authority Effectivity Control Net Change Geometric Dimensioning and Tolerancing Design Control Rules Models Design Manufacturing … Geometric Models 2D 3D CSG, Brep… EDIF, IPC, GDSII compatible “trace” model http://www.ap210.org

14. 14 © Copyright 2005 Manufacturing Product Model (MPM) in an AP210 Standards-Based Engineering Framework XaiTools PWA-B Eagle LKSoft, … Gap-Filling Tools XaiTools PWA-B LKSoft, … Traditional Tools Mentor Graphics Manufacturing Product Model Components STEP AP210 STEP-Book AP210, SDAI-Edit, STI AP210 Viewer,... Instance Browser/Editor PWB Stackup Tool, … Electrical CAD Tools pgpdm Core PDM Tool AP210 interface Doors Slate Systems Engineering Tools - Eurostep AP233 Demonstrator - XaiTools AP233

15. 15 © Copyright 2005 Overall Process -- Circuit Board Stackup Design & Warpage Analysis Using AP210 (WIP) GIT and NIST EEEL in collaboration with AkroMetrix, InterCAX/LKSoft, and Rockwell Collins STEP AP210-based Product Model Identification of warpage “hotspots” on a PCB thickness … width length Multi-Representation Architecture Design-Analysis Integration Methodology Analysis Building Block Model (idealized bodies with effective material properties) PCB Warpage Profile (given: thermal profile + boundary conditions) Validation Measurements in AkroMetrix TherMoiré oven chamber Feedback http://eislab.gatech.edu/projects/

16. 16 © Copyright 2005 Setting up context for warpage analysis APM and ABB Creation Grid (Sieve) Size Single Layer View … Top view of “effective” grid elements in top layer of the PCB … Side view of the PCB with “effective” grid elements across the stratums thickness width length Given: Thermal loading profile Boundary Conditions (mostly displacement) Idealize PWB stackup as a layered shell ABB Model MPM / APM CBAM Effective Material Property Computation CBAM attributes Thermal loading profile Boundary Conditions (mostly displacement) Idealize PWB stackup as a layered shell

17. 17 © Copyright 2005 View of Solution Method Model Layered shell meshGeometric constraints all 6 degrees of freedom locked at midpoint – boundary condition Currently this model is tool-specific (ANSYS). Future possibility of AP209-based implementation exists.

18. 18 © Copyright 2005 -50 C

19. 19 © Copyright 2005 XaiTools PWAB A computer-based framework for multi-fidelity SBD for PWA-B

20. 20 © Copyright 2005 Validation Representing Validation Strategies Metallization Grid Feature BOM JUnit-based Test Framework STEP AP210-based x- ARM instance Simulation and Experimental Results

21. 21 © Copyright 2005 Enablers for Design Enrichment

22. 22 © Copyright 2005 Future Research Analysis  Level of Idealization – Grid Dimensions, Vias,…  Controlled Meshing (non-tool specific)  Printed Circuit Assembly Components Experimental Validation  Initial Conditions and Panelization  Boundary Conditions and Reference Plane Computer-based Engineering Framework

23. 23 © Copyright 2005 Acknowledgements u Georgia Tech –Injoong Kim –Miyako Wilson u LKSoftWare Gmbh –Lothar Klein* –Giedrius Liutkus* –Kasparus Rudokas –Tomas Baltramaitas u Rockwell Collins, Inc. –Michael J. Benda* –David D. Sullivan –William W. Bauer –Mark H. Carlson –Floyd D. Fischer u PDES Inc.Electromechanical Pilot Team* –Greg Smith (Boeing) –Craig Lanning (Northrop Grumman) –Steve Waterbury (NASA)