1. © 2000 Altera Corporation 1 Quartus Simulator

2. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 2 In This Section Simulator –Features –Supported simulation methods –3rd party simulators Simulator settings –Simulation Modes –End Time –Options –Simulation Focus –Saving Simulator Settings

3. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 3 In This Section Continued Creating a Vector Waveform File (.VWF) –Customizing filter –Inserting nodes –Simulation length –Time bars –Creating signal patterns, clocks –Bidirectional pins Simulation –Simulator Report –Comparing waveforms

4. © 2000 Altera Corporation 4 Simulator

5. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 5 Simulator supports 9 different signal values –1Forcing ‘1’ –0Forcing ‘0’ –XForcing unknown –UUninitialized –ZHigh impedance –HWeak ‘1’ –LWeak ‘0’ –WWeak unknown –DCDon’t Care Features

6. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 6 Features Continued Bidirectional pins can be represented as a single signal Easy to use Node Finder –Can customize filter Multiple time bars –Master, relative, and absolute Simulator automatically –Adds output pins to output waveform file –Checks outputs at the end of simulation –Invokes compiler from simulator

7. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 7 Supported Simulation Methods Waveform entry –.vwf (vector waveform file) - primary waveform file for Quartus –.vec (vector file) - MAX+PLUS II.vec file supported for backward compatibility –.tbl (table file) - used to import existing MAX+PLUS II.scf files into Quartus Testbench support –Tcl/TK scripting –Verilog/VHDL 3rd Party Simulators

8. © 2000 Altera Corporation 8 Simulator Settings

9. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 9 Simulation Focus Points to compiler setting on which to focus Specify the design heirarchical entity on which to focus

10. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 10 Saving Simulator Settings Simulator settings determine the type of simulation that is performed Quartus allows simulator settings to be saved Specify the simulator setting 2 Save simulator setting 1 Specify simulator setting on which to focus 3

11. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 11 Simulator End Time Specifies the start time and end time of simulation Enter end time Enter start time Runs simulation to the end of the stimulus file Displays comparison of simulation in simulator report

12. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 12 Simulation Stimulus Specify stimulus file in Simulator Settings Specify stimulus file

13. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 13 Simulator Mode Two modes –Functional Pre-synthesis –Timing Fully compiled netlist Post place and route

14. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 14 Simulator Options Reports ratio of simulated nodes to number of nodes in.vwf file Reports setup and hold time violations in message window Monitors simulation for glitches and reports them in message window Specify time interval that defines Glitch

15. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 15 Running Simulation Select Run Simulation from processing menu

16. © 2000 Altera Corporation 16 Creating Vector Waveform File (.VWF)

17. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 17 Initializing Simulation Reads in simulation netlist

18. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 18 Inserting Nodes Select Insert Node or Bus from Insert Menu with the.VWF file open Click on Node Finder to select nodes

19. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 19 Customizing Filter in Node Finder Filter is used to search for nodes Creates new filter 2 Select netlist 3 Name of filter being customized Select type of node 4 Customize filter 1

20. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 20 Selecting Nodes for Waveform File In Node Finder box enter nodes into Selected Nodes field Select node Enter node into Selected Nodes field Can select entire bus or single bit

21. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 21 Specify Length of Simulation Specify maximum length of simulation time with end time

22. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 22 Inserting Time Bars Set any one time bar to be the master Time bars inserted relative to master or as absolute Specify time bar Set master time bar Time Bar

23. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 23 Drawing Stimulus Waveform Highlight portion of waveform to change Overwrite value with desired value Overwrite value 2 Value shortcut 2 Highlight waveform 1

24. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 24 Creating a Clock Highlight waveform and enter period Clock shortcut 2 Highlight waveform 1 or specify clock period 3 Select a clock defined in Timing Settings 3 Select Clock 2

25. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 25 Creating Counting Pattern Highlight waveform and enter pattern Highlight waveform 1 Pattern shortcut 2 Specify counting frequency 4 Specify counting pattern 3 Specify Radix 3 Select Count Value 2

26. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 26 Assigning Arbitrary Value Highlight waveform and enter constant value for group Highlight waveform 1 Enter value 3 Arbitrary value shortcut 2 Select Arbitrary Value 2

27. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 27 Bidirectional Pins Quartus requires only one pin in the.vwf file Highlight portions of waveform and edit Bidirectional pin

28. © 2000 Altera Corporation 28 Simulation

29. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 29 Simulator Report Displays Simulation Waveform (result waveform) Select to view simulation waveform Opens simulator report Result waveform

30. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 30 Comparing Waveforms With Simulation Waveform open, select Compare to Waveforms under the View menu Select file to be compared against result file Select file

31. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 31 1 Double clicking on message 2 Highlights signal with unexpected value 3 Creates time bar at occurrence of unexpected value Debugging with the Message Window

32. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 32 Compared Waveforms (Simulator Report) ORIGINAL (CTRL+1) ACTUAL (CTRL+2) COMPARED (CTRL+3) (above 2 waveforms are overlapped) RESULTS

33. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 33 Simulating with 3rd Party Simulators Model Technology (ModelSim) Cadence (VERILOG-XL) Viewlogic (VCS) Synopsys (VSS)

34. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 34 Specify Simulator Select EDA Tools Settings menu from the project menu Select Simulation tool

35. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 35 3rd Party Simulators VHDL Simulators –Use Quartus generated.VHO and.SDO files –Use APEX20K_ATOMs.VHD and APEX20K_COMPONENTS.VHD libraries located in the sim_lib directory Verilog Simulators –Use Quartus generated.VO and.SDO files –Use APEX20K_ATOMS.VO library located in the sim_lib

36. © 2000 Altera Corporation Dow load from:www.fpga.com.cn 36 Summary Functional and Timing simulation support Testbench support –Tcl/TKs –Verilog/VHDL Simulation results stored in Simulation report