1. Computer Organization and Design Building a Computer! Montek Singh Nov 18-20, 2015 Lecture 14

2. Building a Computer THIS IS IT! We are now ready to build a computer. We are now ready to build a computer. The ingredients are all in place, so let’s put them together… The ingredients are all in place, so let’s put them together… I wonder where this goes? Instruction Memory A D 0 1 MIPS Kit ALU AB

3. Datapath and Control  Datapath Consists of all of those components that store or process data Consists of all of those components that store or process data Registers, ALU, memories Registers, ALU, memories  Control Consists of those components that tell datapath components what to do and when Consists of those components that tell datapath components what to do and when Clock, control logic (finite state machines or combinational look-up tables) Clock, control logic (finite state machines or combinational look-up tables)

4. Datapath for R-type Instructions  Registers and ALU All of the registers together are called register bank, or “register file” All of the registers together are called register bank, or “register file” Read Reg. 1 (rs) 5 5 5 32 Read Reg. 2 (rt) Write Reg. (rd) Write Data data 1 data 2 3 ALU Operation Inst Bits 25-21 Inst Bits 20-16 Inst Bits 15-11 RegWrite (1 means write, 0 means don’t) 32 ALU

5. Register File  32 registers ($0-$31), each 32 bits wide  2 ports for reading, 1 port for writing Register 0 Register 1 Register 2 Register 3 Register 4 Register... Register 30 Register 31 32 to1 MUX Read Reg 1 Data 1 There are 32 bits in each register! LOT’S OF CONNECTIONS! And this is just one port! Remember, there’s data1 and data2 coming out of the register file! 5 32

6. Register File has 3 ports Read Reg. 1 5 5 5 32 Read Reg. 2 Write Reg. Write Data data 1 data 2 Inst Bits 25-21 Inst Bits 20-16 Inst Bits 15-11 RegWrite 32 2 Read Ports 1 Write Port REALLY LOTS OF CONNECTIONS! This is one reason we have only a small number of registers What’s another reason?

7. Let’s review our ALU  Let’s review the ALU that we built a few lectures ago. Sub Bool Shft Math OP 0 XX 0 1 A+B 1 XX 0 1 A-B X 00 1 0 B >A X 11 1 0 B>>>A X 00 0 0 A & B X 01 0 0 A | B X 10 0 0 A ^ B X 11 0 0 A | B 5-bit ALUFN Flags N,V,C AB Result Bidirectional Shifter Boolean Add/Sub Sub Bool Shft Math 1 0 Z Flag

8. A minor modification to our ALU  Here’s that ALU with a minor modification to support comparisons Sub Bool Shft Math OP 0 XX 0 1 A+B 1 XX 0 1 A-B 1 X0 1 1 A LT B 1 X1 1 1 A LTU B X 00 1 0 B >A X 11 1 0 B>>>A X 00 0 0 A & B X 01 0 0 A | B X 10 0 0 A ^ B X 11 0 0 A | B 5-bit ALUFN Flags N,V,C AB Result Bidirectional Shifter Boolean Add/Sub Sub Bool Shft Math 1 0 Z Flag 0 1 <?

9. Design Approach “Incremental Featurism” We will implement circuits for each type of instruction individually, and merge them (using MUXes, etc). We will implement circuits for each type of instruction individually, and merge them (using MUXes, etc). Our Bag of Components: Registers 0 1 Muxes ALU AB ALU & adders Data Memory WD A RD R/W Register File (3-port) RA1RA2 WA WE WD RD1RD2 Instruction Memory A D Memories +Steps:  1. 3-Operand ALU instrs  2. ALU w/immediate instrs  2. Loads & Stores  3. Jumps & Branches  4. Exceptions (briefly)

10. Review: The MIPS ISA Instruction classes distinguished by types: 1)3-operand ALU 2)ALU w/immediate 3)Loads/Stores 4)Branches 5)Jumps Instruction classes distinguished by types: 1)3-operand ALU 2)ALU w/immediate 3)Loads/Stores 4)Branches 5)Jumps The MIPS instruction set as seen from a Hardware Perspective OP 6 5 55 56 16 26 000000 rsrs rtrt rdrd funcshamt R-type:ALU with Register operands Reg[rd]  Reg[rs] op Reg[rt] 001XXX rsrs rtrt immediate I-type: ALU with constant operand Reg[rt]  Reg[rs] op SEXT(immediate) 10X011 rsrs rtrt immediate I-type: Load and Store Reg[rt]  Mem[Reg[rs] + SEXT(immediate)] Mem[Reg[rs] + SEXT(immediate)]  Reg[rt] I-type: Branch Instructions if (Reg[rs] == Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) if (Reg[rs] != Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) 10X011 immediate rsrs rtrt 00001X 26-bit constant J-type: jump PC  (PC & 0xf0000000) | 4*(immediate)

11. Fetching Sequential Instructions PCPC 4 We will talk about branches and jumps later. flipflop + 32 Read Address Instruction Memory 32

12. Instruction Fetch/Decode  Use a counter to FETCH the next instruction: PROGRAM COUNTER (PC) PROGRAM COUNTER (PC)  use PC as memory address  add 4 to PC, load new value at end of cycle fetch instruction from memory fetch instruction from memory  use some instruction fields directly (register numbers, 16-bit constant) decode rest of the instruction decode rest of the instruction  use bits and to generate controls INSTRUCTION WORD FIELDS PC +4 Instruction Memory A D Control Logic CONTROL SIGNALS 00 OP[31:26], FUNC[5:0] 32

13. 3-Operand ALU Data Path Register File RA1RA2 RD1RD2 WA WD WE Rd: PC +4 Instruction Memory A D Rt: ALU AB ALUFN Control Logic WERF ALUFN WERF 00 32 Rs: 000000 rsrs rtrt rdrd 100XXX00000 R-type:ALU with Register operands Reg[rd]  Reg[rs] op Reg[rt] WERF!

14. Shift Instructions Register File RA1RA2 RD1RD2 WA WD WE Rd: PC +4 Instruction Memory A D Rt: ALU AB ALUFN Control Logic WERF ALUFN WERF 00 32 000000 rsrs rtrt rdrd 000XXXshamt R-type:ALU with Register operands sll: Reg[rd]  Reg[rt] (shift) shamt sllv: Reg[rd]  Reg[rt] (shift) Reg[rs] ASEL Rs: ASEL 10 shamt: ASEL!

15. ALU with Immediate WA PC +4 Instruction Memory A D Rt: Register File RA1RA2 RD1RD2 ALU AB WA WD WE ALUFN Control Logic ALUFN BSEL 01 imm: BSEL WERF 00 BSEL! 001XXX rsrs rtrt immediate I-type: ALU with constant operand Reg[rt]  Reg[rs] op SEXT(immediate) Rd: Rt: 0 10 1 SEXT ASEL BSEL Rs: ASEL 10 shamt: How do you build SEXT? 1  pad with sign 0  pad with 0s

16. Load Instruction WA PC +4 Instruction Memory A D Register File RA1RA2 RD1RD2 ALU AB WA WD WE ALUFN Control Logic Imm: Data Memory RD WD R/W Adr Wr WDSEL 0 1 2 BSEL WDSEL ALUFN Wr WERF 00 32 Rd: Rt: 0 10 1 BSEL SEXT 100011 rsrs rtrt immediate I-type: Load Reg[rt]  Mem[Reg[rs] + SEXT(immediate)] ASEL Rt: Rs: SEXT BSEL 01 SEXT ASEL 10 shamt:

17. Store Instruction WA PC +4 Instruction Memory A D Register File RA1RA2 RD1RD2 ALU AB WA WD WE ALUFN Control Logic Imm: Data Memory RD WD R/W Adr Wr WDSEL 0 1 2 BSEL WDSEL ALUFN Wr WERF 00 32 Rd: Rt: 0 10 1 SEXT ASEL 10X011 rsrs rtrt immediate I-type: Store Mem[Reg[rs] + SEXT(immediate)]  Reg[rt] Rt: BSEL No WERF! Rs: ASEL 10 SEXT BSEL 01 SEXT shamt:

18. JMP Instructions WA PC +4 Instruction Memory A D Register File RA1RA2 RD1RD2 ALU AB WA WD WE ALUFN Control Logic Data Memory RD WD R/W Adr Wr WDSEL 0 1 2 BSEL WDSEL ALUFN Wr J: PCSEL WERF 00 32 PC+4 Rt: Imm: ASEL SEXT 00001X 26-bit constant J-type: j: PC  (PC & 0xf0000000) | 4*(immediate) jal: PC  (PC & 0xf0000000) | 4*(immediate); Reg[31]  PC + 4 PC :J :00 WASEL Rs: ASEL 10 SEXT BSEL 01 SEXT shamt: PCSEL 0123456 WASEL Rd: Rt: 012012 31

19. BEQ/BNE Instructions WA PC +4 Instruction Memory A D Register File RA1RA2 RD1RD2 ALU AB WA WD WE ALUFN Control Logic Data Memory RD WD R/W Adr Wr WDSEL 0 1 2 BSEL WDSEL ALUFN Wr J: PCSEL WERF 00 32 PC+4 Rt: Imm: ASEL SEXT 10X011 immediate rsrs rtrt R-type: Branch Instructions if (Reg[rs] == Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) if (Reg[rs] != Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) + x4 BT Z Z PC :J :00 Why add, another adder? Couldn’t we reuse the one in the ALU? Nope, it needs to do a subtraction. That “x4” unit is trivial. I’ll just wire the input shifted over 2– bit positions. WASEL Rs: ASEL 10 SEXT BSEL 01 SEXT shamt: PCSEL 0123456 WASEL Rd: Rt: 31 012012

20. Jump Indirect Instructions WA PC +4 Instruction Memory A D Register File RA1RA2 RD1RD2 ALU AB WA WD WE ALUFN Control Logic Data Memory RD WD R/W Adr Wr WDSEL 0 1 2 BSEL WDSEL ALUFN Wr J: PCSEL WERF 00 32 PC+4 Rt: Imm: ASEL SEXT R-type: Jump Indirect, Jump and Link Indirect jr: PC  Reg[rs] jalr: PC  Reg[rs], Reg[rd]  PC + 4 Z Z BT WASEL PC :J :00 000000 rsrs rtrt rdrd 00100X 00000 JT Rs: ASEL 10 SEXT BSEL 01 SEXT shamt: PCSEL 0123456 WASEL Rd: Rt: 31 012012 BT + x4

21. Comparisons WA PC +4 Instruction Memory A D Register File RA1RA2 RD1RD2 ALU AB WA WD WE ALUFN Control Logic Data Memory RD WD R/W Adr Wr WDSEL 0 1 2 BSEL WDSEL ALUFN Wr J: PCSEL WERF 00 32 PC+4 Rt: Imm: ASEL SEXT I-type: set on less than & set on less than unsigned immediate slti: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0 sltiu: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0 Z Z BT WASEL PC :J :00 JT 001XXX immediate rsrs rtrt Reminder: To evaluate (A < B) we first compute A-B and look at the flags. LT = N  V LTU = ~C Rs: ASEL 10 SEXT BSEL 01 SEXT shamt: PCSEL 0123456 Rd: Rt: WASEL 31 012012 BT + x4

22. More comparisons WA PC +4 Instruction Memory A D Register File RA1RA2 RD1RD2 ALU AB WA WD WE ALUFN Control Logic Data Memory RD WD R/W Adr Wr WDSEL 0 1 2 BSEL WDSEL ALUFN Wr J: PCSEL WERF 00 32 PC+4 Rt: Imm: ASEL SEXT R-type: set on less than & set on less than unsigned slt: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0 sltu: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0 Z BT WASEL PC :J :00 JT 000000 rsrs rtrt rdrd 10101X 00000 Z Rs: ASEL 10 SEXT BSEL 01 SEXT shamt: PCSEL 0123456 Rd: Rt: BT + x4 WASEL 31 012012

23. LUI WA PC +4 Instruction Memory A D Register File RA1RA2 RD1RD2 ALU AB WA WD WE ALUFN Control Logic Data Memory RD WD R/W Adr Wr WDSEL 0 1 2 BSEL WDSEL ALUFN Wr J: PCSEL WERF 00 32 PC+4 Rt: Imm: ASEL SEXT I-type: Load upper immediate lui: Reg[rt]  Immediate << 16 Z BT WASEL PC :J :00 JT Z 001XXX immediate 00000 rtrt Rs: SEXT BSEL 01 SEXT PCSEL 0123456 Rd: Rt: ASEL 20 shamt: “16” 1 WASEL 31 012012 BT + x4

24. Reset, Interrupts, and Exceptions  Upon reset/reboot: Need to set PC to where boot code resides in memory Need to set PC to where boot code resides in memory  Interrupts/Exceptions: any event that causes interruption in program flow any event that causes interruption in program flow  FAULTS: e.g., nonexistent opcode, divide-by-zero  TRAPS & system calls: e.g., read-a-character  I/O events: e.g., key pressed  How to handle? interrupt current running program interrupt current running program invoke exception handler invoke exception handler return to program to continue execution return to program to continue execution  Registers $k0, $k1 ($26, $27) reserved for operating system (kernel), interrupt handlers reserved for operating system (kernel), interrupt handlers any others used must be saved/restored any others used must be saved/restored

25. Exceptions WA PC +4 Instruction Memory A D Register File RA1RA2 RD1RD2 ALU AB WA WD WE ALUFN Control Logic Data Memory RD WD R/W Adr Wr WDSEL 0 1 2 BSEL WDSEL ALUFN Wr J: PCSEL WERF 00 32 PC+4 Rt: Imm: ASEL SEXT Z BT WASEL PC :J :00 JT Z Rs: SEXT BSEL 01 SEXT PCSEL 0123456 LSEL IRQ 0x80000080 0x80000040 0x80000000 RESET IRQ: Reg[27]  PC+4; PC  0x80000080 Bad Opcode: Reg[27]  PC+4; PC  0x80000040 Reset: PC  0x80000000 ASEL 20 shamt: “16” 1 WASEL Rd: Rt: 01230123 31 27 BT + x4

26. MIPS: Our Final Version This is a complete 32-bit processor. Although designed in “one” class lecture, it executes the majority of the MIPS R2000 instruction set. Executes one instruction per clock BT + x4 WASEL Rd: Rt: 01230123 31 27

27. MIPS Control  The control unit is simply a large truth table Instruction RESETRESET IRQIRQ PCSELPCSEL SEXTSEXT WASELWASEL WDSELWDSEL ALUFN Sub Bool Shift Math WRWR WERFWERF ASELASEL BSELBSEL X1X4000000000000 X0160300 000000 add000001000010100 sll andi lw sw beq Problem Set #4!

28. Summary  We have designed a full “miniMIPS” processor! has datapath, which includes registers, ALU has datapath, which includes registers, ALU instruction and data memories instruction and data memories control unit governs everything! control unit governs everything!  Next couple of classes: some advanced topics memory hierarchy: caches etc. memory hierarchy: caches etc. pipelining the processor: benefits and challenges pipelining the processor: benefits and challenges wrap up (grades etc.) wrap up (grades etc.)  Don’t forget: Problem Set #4