1. Physical Properties of Logic Devices Technician Series Created Mar 2015 ©prgodin@gmail.com 1

2. Timing Measurements Timing is a critical issue in digital electronics. Much of the specification sheet for logic devices is devoted to timing specifications. Different families of devices require different measurements. 2

3. Waveform Measurement 90% 10% 50% Rise Time (t R ) Fall Time (t F ) Pulse Separation (Ps) Pulse Width (Pw) Period (T) Rise and fall times are typically measured in nanoseconds (ηs) Amplitude 3

4. Typical Waveform Due to the effects of inductance, capacitance, noise, grounding, device properties and other factors, digital signals tend to be electrically and timely less than perfect. These effects are increased with frequency. Typical Waveform Over-shoot Pre-shoot Ringing Rise time Fall time Droop 4

5. Timing problems cause glitches in Asynchronous counters 0000111 11 1 10 1 0 0000 000 010 000 100 0 0 1 5

6. Propagation Delay 6

7. Propagation Delay is defined as the amount of time it takes after an input signal is applied for the output to change. Propagation Delay is caused by: o Electron Speed in the medium o Capacitance Propagation delay is usually measured in  seconds Prop Delay varies by logic Family A B 7

8. Propagation Delay Propagation delay specifications state the direction of the output pulse edge. T pLH : Time Low to High change in output T pHL : Time High to Low change in output Prop delay measurements are different for CMOS and TTL devices. 8

9. Propagation Delay CMOS measured at 50% mark TTL measured at 1.5 Volt mark 9

10. Propagation Delay Typical propagation delays: o TTL (7400) T pLH : 11  s typical, 22  s maximum T pHL : 7  s typical, 15  s maximum o TTL (74S00) T pLH : 3  s typical, 4.5  s maximum T pHL : 3  s typical, 5  s maximum o CMOS (4011B) T pLH : 125  s typical, 250  s maximum T pHL : 125  s typical, 250  s maximum 10

11. Example 1 Determine the propagation delay for the following circuit, assuming T pLH : 11  s typical, 22  s maximum and T pHL : 7  s typical, 15  s maximum. Total Delay T pLH + T pHL + T pLH = 22  s + 15  s + 22  s = 59  s T pHL + T pLH + T pHL = 15  s + 22  s + 15  s = 52  s Total Propagation Delay is 59  s Worst case is used to predict the propagation delay 11

12. Input/Output Current 12

13. Gate Currents Digital Logic devices are constructed from analog components which include a variety of transistors, resistors, diodes and other semiconductors. TTL devices, based on transistors, rely on current flow to sense the input logic. Current flow between the output of one device and the input of the other device is required to switch the transistors on or off. The action of the transistors is what determines the output logic state. 13

14. Source and Sink Every logic device will either source or sink current. o When the gate output is in a high state, it sources current. Sourcing = provides current o When the gate output is in a low state, it sinks current. Sinking = receives current o Gate inputs can either sink or source current, depending on the level of the output attached to it. Current entering a gate is + (sink) Current exiting a gate is - (source) 14

15. Source and Sink Output sinks current in a low state Output sources current in a high state 15

16. Driving and Loading Driving gate: A gate that provides a logic level to other gates. Loading gate: A gate that receives a logic level from other gates. Driving Gate Loading Gates 16

17. Input and Output Current I IL : Input Low Current. Current when input is in a low state. I IH : Input High Current. Current when input is in a high state. I OL : Output Low Current. Current when output is in a low state. I OH : Output High Current. Current when output is in a high state. 17

18. Input and Output Current 18

19. Typical Current Values 7400: o I IL :-1.6mA o I IH : 40  A o I OL :16mA o I OH : -0.4mA 74LS00: o I IL :-0.4mA o I IH : 20  A o I OL :8mA o I OH : -0.4mA 19

20. Power 20

21. Some Definitions Quiescent: output logic that is not changing (also known as static) Dynamic: output logic that changes (also known as switching) V CC : TTL Supply Voltage I CC : TTL Supply Current I CCH : TTL Supply Current with all outputs high. I CCL : TTL Supply Current with all outputs low. V DD : CMOS Supply Voltage V SS : CMOS Ground I DD : CMOS Supply Current (static/quiescent) I T : CMOS Supply Current (static and dynamic) C PD : CMOS Internal Capacitance 21

22. Power (TTL) Power = Voltage  Current = V CC  I CC Vcc & Icc 22

23. Device Input Current (TTL) With all the outputs = logic high Input current = I CCH specification I CCH 11 11 Make the outputs logic high by applying the appropriate input logic 23

24. Device Input Current (TTL) With all the outputs = logic low Input current = I CCL specification I CCL 00 00 Make the outputs logic low by applying the appropriate input logic 24

25. Power = Voltage  Current = V CC  I CC If all gates are high: o Pd = V CC  I CCH o I CC = I CCH If all gates are low: o Pd = V CC  I CCL o I CC = I CCL TTL Power Calculation Assume Vcc = 5V, unless otherwise specified 25

26. Device input current (TTL) I CC DC=25% 0 00 In this example, ¼ of the gates are at 25% duty cycle, ¾ are logic low. Pd= Vcc(¼@(0.25  I CCH +0.75  I CCL ) + (¾ @ I CCL )) Pd= Vcc((0.25  (0.25  I CCH +0.75  I CCL ) + (0.75  I CCL )) Remember: A duty cycle of 25% means that the output is high for 25% of the time (using I CCH ), and low for 75% of the time (using I CCL ). 26

27. CMOS Power CMOS uses very little power in the static state (in the order of  W). As switching increases (more dynamic), so does power consumption. This is primarily due to capacitance. Power requirements also increase with ambient temperature. As temperature increases, so does power consumption. Static power consumption for a B-Series gate  500  W maximum Other families of CMOS have lower power consumption. 27

28. CMOS Power Calculation Most CMOS specification sheets provide the mathematical equation for calculating power consumption. Care must be taken when utilizing the specification sheet. o Current is specified per gate or per IC package. Read carefully. o Formulas may vary (example: 4011B compared to the 4027B) o I DD is different from I T Generally: 28

29. Input/Output Voltages 29

30. Voltage and Logic Values Digital logic is represented as a voltage value. We are accustomed to assuming the following: o Logic high = 5V o Logic Low = 0V In reality: o Applied voltage values, and the resultant logic highs and lows, vary by device family. Some logic operates on 3.3 Volts, others on 12 Volts and yet other applications operate on a +12/-12 Volt logic. o many digital logic devices produce logic values that are not ideal. 30

31. Voltage Issues When designing systems, we must ensure that the logic voltage output of a (driving) gate will be interpreted properly by the receiving (loading) gate. Vcc 1 Vcc 2 31

32. Output Voltage Specifications V OH : Voltage Output High. o Minimum voltage produced for a high state. V OL : Voltage Output Low. o Maximum voltage produced for a low state. Output Voltage Minimum Maximum V OH V OL Some TTL logic high outputs can be as little as 2.4 volts (on a 5 Volt system). 32

33. Input Voltage Specifications V IH : Voltage Input High. o Minimum voltage required for a high state. V IL : Voltage Input Low. o Maximum voltage required for a low state. Minimum Maximum V IH V IL Input Voltage 33

34. Voltage Output/Input V OH V OL V IH V IL Undefined V CC Ground Undefined OutputInput Minimum Maximum Gate inputs that receive voltage levels within the undefined zone are unable to reliably determine the logic level. 34

35. IC’s must have minimum and maximum criteria for output levels. o For output, the high must have a minimum acceptable voltage level o For output, the low must have a maximum acceptable voltage level IC’s must have minimum and maximum criteria for input levels o For input, the high must have a minimum acceptable voltage level o For input, the low must have a maximum acceptable voltage level Voltage Characteristics 35

36. Noise Margin 36

37. Noise Noise: Unwanted electrical signal. Noise Margin: The ability to tolerate noise. o Noise margin defines the difference between the worst-case voltage output and input levels. CMOS devices have larger input logic level ranges, making them less susceptible to noise. 37

38. Voltage Output/Input OutputInput V OH V OL V IH V IL Undefined V CC Ground Undefined Minimum Maximum Noise Margin 38

39. Noise Anticipated Signal Actual Signal with Noise Undefined Output LOW HIGH Undefined LOW HIGH Undefined Input 39

40. Improved Noise Margin Anticipated Signal Actual Signal with Noise Output LOW HIGH Undefined LOW HIGH Undefined Input 40

41. Noise Margin Calculation Noise Margin is the difference between the worst-case output voltages to the worst-case input levels. 41

42. Noise Margin Example 4011B: o V OH : 4.95 V o V OL : 0.05 V o V IH : 3.5 V o V IL : 1.5 V OutputInput Minimum Maximum 4.95 V 0.05 V 3.5 V 1.5 V Noise Margin 42

43. Noise Margin Example 7400: o V OH : 2.4 V o V OL : 0.4 V o V IH : 2 V o V IL : 0.8 V OutputInput Minimum Maximum 2.4 V 0.4 V 2 V 0.8 V Noise Margin 43

44. Interfacing CMOS and TTL Although CMOS and TTL device families have different electrical characteristics, they can be interfaced. Fanout and Noise Margin are characteristics that must be accounted for in the design process. Propagation delay and power are other important considerations. 44

45. CMOS TO TTL 45

46. CMOS TTL Noise Margin Calculation CMOS 4011B: o V OH : 4.95 V o V OL : 0.05 V TTL 74LS04 o V IH : 2V o V IL : 0.8V 46

47. CMOS 4011B: o V OH : 4.95 V o V OL : 0.05 V TTL 74LS04 o V IH : 2V o V IL : 0.8V CMOS TTL Noise Margin Calculation 47

48. With a V nH of +2.95V and a V nL of +0.75V, there are no noise margin problems with this circuit design. CMOS TTL Noise Margin Calculation CMOS TTL OutputInput Minimum=4.95V Minimum=2.0V Maximum=0.05V Maximum=0.8V 48

49. CMOS 4011B: –I OH : -0.51mA –I OL : 0.51mA TTL 74LS04 –I IH : 20  A –I IL : -0.4mA CMOS TTL Noise Margin Calculation 49

50. Worst-case = 1 gate input CMOS TTL Noise Margin Calculation 50

51. Most CMOS devices can drive at least 1 TTL input from either the voltage or current perspective. Read the introduction in the specification sheet for the CMOS device. CMOS TTL Noise Margin Calculation 51

52. TTL to CMOS 52

53. CMOS 4011B: o V IH : 3.5 V o V IL : 1.5 V TTL 74LS04 o V OH : 2.7V o V OL : 0.5V TTL CMOS Noise Margin Calculation 53

54. CMOS 4011B: o V IH : 3.5 V o V IL : 1.5 V TTL 74LS04 o V OH : 2.7V o V OL : 0.5V Voltage Problem TTL CMOS Noise Margin Calculation 54

55. There is a problem with the noise margin. CMOS TTL Output Input Minimum=3.5V Minimum=2.7V Maximum=1.5V Maximum=0.5V TTL CMOS Noise Margin Calculation 55

56. The V OH of the TTL gate is too low for the CMOS gate to reliable determine a high input. TTL CMOS Noise Margin Calculation 56

57. In-Class Discussion Interface Circuits: o Improve Current o Improve Noise Margin o Shift Voltages o Switch Loads o Operate with positive and negative logic o Dealing with LED Loads (review) 57

58. Conclusion When mixing logic families, it is important to: review the specification sheets make the necessary calculations to ensure the devices will function properly utilize interfacing devices if needed 58

59. Review Questions What is the difference between: o Loading and Sinking inputs o Driving and Sourcing inputs o Fanout and Noise Margin o I CC and I CCH o I DD and I T 59

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