1. Mid-Term Presentation February 28, 2008

2. Team Members Charlie Mraz EE Team Leader Analog Design PCB Layout Allen Joiner EE Power Supply Purchasing/Finance James Sakalaukus CPE FPGA Implementation Scott Wilson CPE PIC Implementation Website Design

3. Overview Introduction Team Problem/Solution Constraints Economic Manufacturability Design Refinements Analog FPGA Microprocessor Power Supply Test Plan Packaging PCB Enclosure

4. Problem Test Equipment is Expensive Oscilloscopes and Function Generators are Chained to University Lab Benches Opportunity to Learn, Experiment, or Work is Limited to School or Work Hours Students, Hobbyists, and Small Businesses Cannot Afford to Purchase Their Own Equipment

5. Solution PC-Based Oscilloscope / Function Generator External Device can be Small and Inexpensive Leverages Computing Resources of any PC with a USB Port Graphical User Interface Standard Scope Probe Inputs and Function Generator Output Data can be Saved and Processed “Off-Line” by Excel, MATLAB, or other Analysis Tools

6. The Competition Bitscope BS310U [1] Stingray DS1M12 [2] DAWGi Sample Rate 40MSa/s1MSa/s60MSa/s Analog Bandwidth 100MHz250kHz30MHz Max. Input Voltage 208Vp-p10Vp-p20Vp-p Price$515.00$220.00$199.00

7. Constraints Practical Constraints Cost Manufactured for around $150 Sold for Around $200 Comparable products have an MSRP of up to $515 Ease of Assembly No Leadless Packages like BGA, CSP, etc. Components on Top of Board Only

8. Design Refinements Analog Signal Conditioning New Op-Amps from TI PSPICE Models Allowed Improved Simulations JFET-Input Probe Buffer Improves Performance With Attenuating Probes High-Speed Current-Feedback Op-Amps in the High- Gain Stages Provide Increased Bandwidth at Higher Gains Simulation Parameters Fine-Tuned for Maximum Gain Flatness

9. Simulated Performance Input Gain of 20: -0.1dB @ 32MHz -0.5dB @ 47MHz -1dB @ 56MHz

10. Prototype Performance FrequencyMagnitude (V)Gain (dB) 1 kHz2.0010 1 MHz1.981-0.09 10 MHz1.921-0.35 20 MHz1.701-1.41 NOTE: Measurements taken at overall gain of 20

11. Simulated Performance Output Gain of 10: +0.1dB @ 22MHz -0.5dB @ 103MHz -1dB @ 111MHz

12. Design Refinements FPGA Design Migrated from Dev. Board to PCB Spartan 3E Family Device Chosen to Maximize Resource/Cost Ratio Dedicated Clock Nets Used to Improve Max Clock Rate I/O Banking Improved Minimal Changes Required in Logic Design

13. Design Refinements Microprocessor PIC18F65J50 Chosen For Production Design Lower Cost - $3.01 vs. $4.38 for 18LF4550 More I/Os Two EUSARTs Allow Separate SPI Interfaces for Analog Components and FPGA Minimal Changes Required in Code

14. Design Refinements Power Supply Dedicated Power Supply Circuits Replace Prototype’s Bench Supply/Wall Wart Combination Seven Individual Voltage Rails: +/-12V, +/-3.3V, +3.3V, +2.5V, +1.2V Generates 2.048V and 1.024V Precision References AC Wall Transformer and Half-Wave Rectifier Front End Linear Regulators Throughout

15. Test Plan Oscilloscope Bandwidth Test Voltage Test Function Generator Bandwidth Test Voltage Test Waveform Test

16. Oscilloscope Bandwidth Test Input Signal must be within -1dB at 30MHz Must sample the signal at 60MSa/s

17. Oscilloscope Voltage Test Must be capable of handling a 20V Peak to Peak Signal through a 10x probe 2 Volt Input Naked

18. Function Generator Bandwidth Test Signal must be -1dB at 30MHz Signal must be sampled at 60MSa/s

19. Function Generator Voltage Test Must output a 10V Peak to Peak Signal Must drive a 50Ω Load

20. Function Generator Waveform Test Must Display four waveforms Sine wave Square wave Triangle wave Sawtooth wave

21. Enclosure Extruded Aluminum Case 6.3" L x 4.06" W x 1.2" H Rails for 100mm wide PCB Plastic Bezel 3 – BNC Connectors 1 – USB Mini B Connector 1 – 2.1mm Power Connector 3 – Toggle Switches [1] [3] [5] [4] [2]

22. PCB Four Layer Board Separate ground and power planes Spilt ground plane and split power plane Reduce Noise Everything is on one board Easy assembly No wires No board to board connectors Board will just slide into enclosure on the rails

23. PCB BNC Connectors Power Connector USB Connector Input Stages Output Stage FPGAMicrocontroller BFCs

24. Conclusion Team Redistribution Constraints Design Refinements Test Plan Packaging Questions???

25. References [1]Hammond, “1455L1601”, 2007. [Online]. Available: http://www.hammondmfg.com/pdf/1455L1601.pdf [Accessed February. 27, 2008]. [2](26, Febrary 2008) DigiKey. [Online] Available: http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=A32261- ND [3](26, Febrary 2008) DigiKey. [Online] Available: http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=360- 1792-ND [4](26, Febrary 2008) DigiKey. [Online] Available: http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=CP- 002APJ-ND [5](26, Febrary 2008) DigiKey. [Online] Available: http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=WM171 15-ND