1. MicroProcessors Lec. 4 Dr. Tamer Samy Gaafar

2. Course Web Page http://www.tsgaafar.faculty.zu.edu.eg — Email: tsgaafar@yahoo.com

3. Consider a computer with 4 32-bit registers R1-R4. a program counter PC, and a stack pointer SP. All instructions are of the form: OPERATION OPERAND1, OPERAND2. OPERATION is a function such as ADD, MOVE, and MULT. OPERAND1 is one operand, and OPERAND2 is a second operand. The destination operand is always OPERAND2. Suppose the computer executes the program shown on the right. Instructions are 32-bit. Quiz

4. ADD R1,(R4) MULT (R4),R2 MOVE (R2),200 ADD (R4), R3 Copy the table below in your answer sheet and fill in the contents of each register, memory location, and condition code after the execution of each individual instruction.

5. Outline Integer Representation —Sign-Magnitude, Two’s Complement Integer Arithmetic —Negation, Addition, Subtraction —Multiplication, Division Floating-Point Representation Floating-Point Arithmetic

6. Arithmetic & Logic Unit (ALU) Does the calculations. Everything else in the computer is there to service this unit. Handles integers. Handles real (floating point) numbers.

7. ALU Inputs and Outputs Data Results e.g., overflow flag Operation & data in/out Registers Control unit Flags

8. Integer Representation General-case number: –548.923 Only have 0 & 1 to represent everything. — No minus sign. — No period (radix point). Positive integer numbers are stored in binary. — An 8-bit word can represent the numbers: — e.g., 41=00101001 Signed integer numbers — Sign-Magnitude — Two’s complement 0 - 255

9. Sign-Magnitude vs. 2’s Complement Decimal Representation Sign-Magnitude Representation 2’s Complement Representation +8 +7 +6 +5 +4 +3 +2 +1 +0 -0 -2 -3 -4 -5 -6 -7 -8 -- 0111 0110 0101 0100 0011 0010 0001 0000 1001 1010 1011 1100 1101 1110 1111 -- 1000 -- 0111 0110 0101 0100 0011 0010 0001 0000 1111 1010 1101 1100 1011 1110 1001 1000 -- (-A) 10  2 4 – A(-A) 10  2 4-1 + A

10. Sign-Magnitude Representation Left most bit is sign bit. —0 means positive. —1 means negative. Example:  +18 = 00010010  –18 = 10010010 Problems — Need to consider both sign and magnitude in arithmetic. — Two representations of zero (+0 and –0)  more difficult to test for 0.  one wasted bit combination!

11. Two’s Complement Representation Like sign-magnitude representation, leftmost bit is used as a sign bit. Differs from sign-magnitude representation in how the remaining bits are interpreted. Positive number: convert to binary Negative number: 2’s complement e.g., 8-bit 2’s complement representation +3 = 00000011 +2 = 00000010 +1 = 00000001 +0 = 00000000 –1 = 11111111 –2 = 11111110 –3 = 11111101

12. n-bit Two’s Complement Representation Length of number (in bits) is first specified. Assume n-bit numbers. We have 2 n different combinations of size n bits  we can represent 2 n different numbers. Assign the value 0 to the combination 00…0. We have 2 n –1 different combinations left. Assign the values 1, 2, …, 2 n–1 –1 to 1, 2,.., 2 n–1 –1. Assign the values –2 n–1, –2 n–1 +1, …, –1 to 2 n–1, 2 n–1 +1, …, 2 n –1 Getting the 2’s comp. of A is equivalent to 2 n – A –2 n – 1 ≤ A ≤ 2 n – 1 – 1

13. Characteristics of 2’s Comp. Rep. & Arithmetic 1’s complement Consider n-bit 2’s complement representation Equivalent to: 2 n – A

14. Benefits One representation of zero. Arithmetic works easily (see later). Negating is fairly easy — 3 = 00000011 — Boolean (one’s) complement gives 11111100 — Add 1 to LSB 11111101 — This is equivalent to 2 8 – 3 = 253 = 11111101 2’s complement of 3

15. Conversion between 2’s Comp. & Decimal Value Box 0 +8 Result obtained using value box is correct because:  Sign bit is 1  Number = -(2’s comp. of 10000011) = -(2 8 - 10000011) = -125

16. Conversion Between Lengths Positive numbers  pack with leading zeros  +18 = 00010010  +18 = 00000000 00010010 Negative numbers  pack with leading ones  -18 = 10010010  -18 = 11111111 10010010 i.e. pack with MSB (sign bit)  Sign extension

17. Addition and Subtraction Addition  Normal binary addition.  Monitor sign bit for overflow. Subtraction  Take two’s complement of subtrahend and add to minuend  A – B = A + (–B) So we only need addition and complement circuits.

18. Addition of Numbers in 2’s Comp. Rep. 4-bit 2’s comp. rep. 4-bit 2’s comp. representation

19. Binary Addition/Subtraction Logic Circuit. Addition  Add/sub control = 0. Subtraction  Add/sub control = 1

20. At the stage i: Input: x i is i th bit of x y i is i th bit of y c i is carry-in from stage i-1 Output: s i is the sum c i+1 carry-out to stage i+1 1-Bit Addition (Full Adder)

21. Full Adder (FA): Symbol for the complete circuit for a single stage of addition. Addition Logic for a Single Stage SumCarry

22. An n-bit Ripple-Carry Adder Cascade n full adder (FA) blocks to form a n-bit adder. Carries propagate or ripple through this cascade  n-bit ripple carry adder. Carry-in c 0 into the LSB position provides a convenient way to perform subtraction.

23. Cascade of k n-bit Adders k n-bit numbers can be added by cascading k n-bit adders. Each n-bit adder forms a block, so this is cascading of blocks. Carries ripple or propagate through blocks  Blocked Ripple Carry Adder.