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Interconnect Terminal Mapping Figures 30 Sep 2015 1
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Legend Connected Pads Connected Pins Shorted Pins Model Subcircuit Ideal Connection Buffer A1 A2 A3 A4 B1 B2 B3 B4 PU(A1) PD(A1) A1 2
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Subckt 1 – Package + Die, Each Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 POWER pins GND pins Signal pin A1 Signal pin A2.subckt PkgDie4P4G2Sig 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Buffer A1 Buffer A2 PU PD PU PD sig 3
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Subckt 1 Connections, by pin_name A1 P1 P2 P3 P4 G1 G2 G3 G4 A2 [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 [Begin Interconnect Model] … 1 Pin_I/O pin_name A1 2 Pin_rail pin_name P1 3 Pin_rail pin_name P2 4 Pin_rail pin_name P3 5 Pin_rail pin_name P4 6 Pin_rail pin_name G1 7 Pin_rail pin_name G2 8 Pin_rail pin_name G3 9 Pin_rail pin_name G4 10 Pin_I/O pin_name A2 11 Puref pin_name A1 12 Buffer_I/O pin_name A1 13 Pdref pin_name A1 14 Puref pin_name A2 15 Buffer_I/O pin_name A2 16 Pdref pin_name A2 [End Interconnect Model] PU(A1) PD(A1) A1 PU(A2) PD(A2) A2.subckt PkgDie4P4G2Sig 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 4
![Subckt 1 Connections, by pin_name A1 P1 P2 P3 P4 G1 G2 G3 G4 A2 [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND [Begin Interconnect Model] … 1 Pin_I/O pin_name A1 2 Pin_rail pin_name P1 3 Pin_rail pin_name P2 4 Pin_rail pin_name P3 5 Pin_rail pin_name P4 6 Pin_rail pin_name G1 7 Pin_rail pin_name G2 8 Pin_rail pin_name G3 9 Pin_rail pin_name G4 10 Pin_I/O pin_name A2 11 Puref pin_name A1 12 Buffer_I/O pin_name A1 13 Pdref pin_name A1 14 Puref pin_name A2 15 Buffer_I/O pin_name A2 16 Pdref pin_name A2 [End Interconnect Model] PU(A1) PD(A1) A1 PU(A2) PD(A2) A2.subckt PkgDie4P4G2Sig](http://images.slideplayer.com./32/9930258/slides/slide_4.jpg "Subckt 1 Connections, by pin_name A1 P1 P2 P3 P4 G1 G2 G3 G4 A2 [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND [Begin Interconnect Model] … 1 Pin_I/O pin_name A1 2 Pin_rail pin_name P1 3 Pin_rail pin_name P2 4 Pin_rail pin_name P3 5 Pin_rail pin_name P4 6 Pin_rail pin_name G1 7 Pin_rail pin_name G2 8 Pin_rail pin_name G3 9 Pin_rail pin_name G4 10 Pin_I/O pin_name A2 11 Puref pin_name A1 12 Buffer_I/O pin_name A1 13 Pdref pin_name A1 14 Puref pin_name A2 15 Buffer_I/O pin_name A2 16 Pdref pin_name A2 [End Interconnect Model] PU(A1) PD(A1) A1 PU(A2) PD(A2) A2.subckt PkgDie4P4G2Sig")
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Subckt 2 – Package + Die, Merged Pins 12341234 567567 8 POWER pins (4) GND pins (4) Signal pin A1 Signal pin A2 Buffer A1 Buffer A2 PU(2) PD(2) sig.subckt PkgDie1P1G2Sig 1 2 3 4 5 6 7 8 5
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Subckt 2 Connections, I/O by pin_name, POWER/GND by bus_label A1 P1 P2 P3 P4 A2 G1 G2 G3 G4 [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND 12341234 657657 8 [Begin Interconnect Model] … 1 Pin_I/O pin_name A1 2 Pin_rail bus_label VDDbus 3 Pin_I/O pin_name A2 4 Pin_rail bus_label VSSbus 5 Buffer_I/O pin_name A1 6 Buffer_rail bus_label VDDbus 7 Buffer_rail bus_label VSSbus 8 Buffer_I/O pin_name A2 [End Interconnect Model] [Pin Mapping] pulldown_ref pullup_ref A1 VSSbus VDDbus A2 VSSbus VDDbus P1 VSSbus NC P2 VSSbus NC P3 VSSbus NC P4 VSSbus NC G1 NC VDDbus G2 NC VDDbus G3 NC VDDbus G4 NC VDDbus PU(A1) PD(A1) A1 PU(A2) PD(A2) A2.subckt PkgDie1P1G2Sig 1 2 3 4 5 6 7 8 6
![Subckt 2 Connections, I/O by pin_name, POWER/GND by bus_label A1 P1 P2 P3 P4 A2 G1 G2 G3 G4 [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND [Begin Interconnect Model] … 1 Pin_I/O pin_name A1 2 Pin_rail bus_label VDDbus 3 Pin_I/O pin_name A2 4 Pin_rail bus_label VSSbus 5 Buffer_I/O pin_name A1 6 Buffer_rail bus_label VDDbus 7 Buffer_rail bus_label VSSbus 8 Buffer_I/O pin_name A2 [End Interconnect Model] [Pin Mapping] pulldown_ref pullup_ref A1 VSSbus VDDbus A2 VSSbus VDDbus P1 VSSbus NC P2 VSSbus NC P3 VSSbus NC P4 VSSbus NC G1 NC VDDbus G2 NC VDDbus G3 NC VDDbus G4 NC VDDbus PU(A1) PD(A1) A1 PU(A2) PD(A2) A2.subckt PkgDie1P1G2Sig](http://images.slideplayer.com./32/9930258/slides/slide_6.jpg "Subckt 2 Connections, I/O by pin_name, POWER/GND by bus_label A1 P1 P2 P3 P4 A2 G1 G2 G3 G4 [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND [Begin Interconnect Model] … 1 Pin_I/O pin_name A1 2 Pin_rail bus_label VDDbus 3 Pin_I/O pin_name A2 4 Pin_rail bus_label VSSbus 5 Buffer_I/O pin_name A1 6 Buffer_rail bus_label VDDbus 7 Buffer_rail bus_label VSSbus 8 Buffer_I/O pin_name A2 [End Interconnect Model] [Pin Mapping] pulldown_ref pullup_ref A1 VSSbus VDDbus A2 VSSbus VDDbus P1 VSSbus NC P2 VSSbus NC P3 VSSbus NC P4 VSSbus NC G1 NC VDDbus G2 NC VDDbus G3 NC VDDbus G4 NC VDDbus PU(A1) PD(A1) A1 PU(A2) PD(A2) A2.subckt PkgDie1P1G2Sig")
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Subckt 2 Connections, I/O by pin_name, POWER/GND by bus_label and signal_name [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND [Begin Interconnect Model] … 1 Pin_I/O pin_name A1 2 Pin_rail signal_name VDD 3 Pin_I/O pin_name A2 4 Pin_rail signal_name VSS 5 Buffer_I/O pin_name A1 6 Buffer_rail bus_label VDDbus 7 Buffer_rail bus_label VSSbus 8 Buffer_I/O pin_name A2 [End Interconnect Model].subckt PkgDie1P1G2Sig 1 2 3 4 5 6 7 8 A1 P1 P2 P3 P4 A2 G1 G2 G3 G4 12341234 657657 8 PU(A1) PD(A1) A1 PU(A2) PD(A2) A2 7 [Pin Mapping] pulldown_ref pullup_ref A1 VSSbus VDDbus A2 VSSbus VDDbus P1 VSSbus NC P2 VSSbus NC P3 VSSbus NC P4 VSSbus NC G1 NC VDDbus G2 NC VDDbus G3 NC VDDbus G4 NC VDDbus
![Subckt 2 Connections, I/O by pin_name, POWER/GND by bus_label and signal_name [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND [Begin Interconnect Model] … 1 Pin_I/O pin_name A1 2 Pin_rail signal_name VDD 3 Pin_I/O pin_name A2 4 Pin_rail signal_name VSS 5 Buffer_I/O pin_name A1 6 Buffer_rail bus_label VDDbus 7 Buffer_rail bus_label VSSbus 8 Buffer_I/O pin_name A2 [End Interconnect Model].subckt PkgDie1P1G2Sig A1 P1 P2 P3 P4 A2 G1 G2 G3 G PU(A1) PD(A1) A1 PU(A2) PD(A2) A2 7 [Pin Mapping] pulldown_ref pullup_ref A1 VSSbus VDDbus A2 VSSbus VDDbus P1 VSSbus NC P2 VSSbus NC P3 VSSbus NC P4 VSSbus NC G1 NC VDDbus G2 NC VDDbus G3 NC VDDbus G4 NC VDDbus](http://images.slideplayer.com./32/9930258/slides/slide_7.jpg "Subckt 2 Connections, I/O by pin_name, POWER/GND by bus_label and signal_name [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND [Begin Interconnect Model] … 1 Pin_I/O pin_name A1 2 Pin_rail signal_name VDD 3 Pin_I/O pin_name A2 4 Pin_rail signal_name VSS 5 Buffer_I/O pin_name A1 6 Buffer_rail bus_label VDDbus 7 Buffer_rail bus_label VSSbus 8 Buffer_I/O pin_name A2 [End Interconnect Model].subckt PkgDie1P1G2Sig A1 P1 P2 P3 P4 A2 G1 G2 G3 G PU(A1) PD(A1) A1 PU(A2) PD(A2) A2 7 [Pin Mapping] pulldown_ref pullup_ref A1 VSSbus VDDbus A2 VSSbus VDDbus P1 VSSbus NC P2 VSSbus NC P3 VSSbus NC P4 VSSbus NC G1 NC VDDbus G2 NC VDDbus G3 NC VDDbus G4 NC VDDbus")
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Subckt 3 – Package + Die, Merged Pins, Power/GND Only Model 1212 3434 POWER pins (4) GND pins (4).subckt PkgDie1P1G 1 2 3 4 PU(2) PD(2) 8
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Subckt 3 Connections, Ideal I/O, POWER/GND by signal_name and bus_label A1 P1 P2 P3 P4 G1 G2 G3 G4 A2 [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND 1212 3434 [Begin Interconnect Model] … 1 Pin_rail signal_name VDD 2 Pin_rail signal_name VSS 3 Buffer_rail bus_label VDDbus 4 Buffer_rail bus_label VSSbus [End Interconnect Model] PU(A1) PD(A1) A1 PU(A2) PD(A2) A2 Tool connects signals as it would without interconnect model.subckt PkgDie1P1G 1 2 3 4 [Pin Mapping] pulldown_ref pullup_ref A1 VDDbus VSSbus A2 VDDbus VSSbus 9 Discussed 30 Sep 2015: This slide should be replaced with one showing separate [Pin] RLC circuits for I/Os.
![Subckt 3 Connections, Ideal I/O, POWER/GND by signal_name and bus_label A1 P1 P2 P3 P4 G1 G2 G3 G4 A2 [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND [Begin Interconnect Model] … 1 Pin_rail signal_name VDD 2 Pin_rail signal_name VSS 3 Buffer_rail bus_label VDDbus 4 Buffer_rail bus_label VSSbus [End Interconnect Model] PU(A1) PD(A1) A1 PU(A2) PD(A2) A2 Tool connects signals as it would without interconnect model.subckt PkgDie1P1G [Pin Mapping] pulldown_ref pullup_ref A1 VDDbus VSSbus A2 VDDbus VSSbus 9 Discussed 30 Sep 2015: This slide should be replaced with one showing separate [Pin] RLC circuits for I/Os.](http://images.slideplayer.com./32/9930258/slides/slide_9.jpg "Subckt 3 Connections, Ideal I/O, POWER/GND by signal_name and bus_label A1 P1 P2 P3 P4 G1 G2 G3 G4 A2 [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND [Begin Interconnect Model] … 1 Pin_rail signal_name VDD 2 Pin_rail signal_name VSS 3 Buffer_rail bus_label VDDbus 4 Buffer_rail bus_label VSSbus [End Interconnect Model] PU(A1) PD(A1) A1 PU(A2) PD(A2) A2 Tool connects signals as it would without interconnect model.subckt PkgDie1P1G [Pin Mapping] pulldown_ref pullup_ref A1 VDDbus VSSbus A2 VDDbus VSSbus 9 Discussed 30 Sep 2015: This slide should be replaced with one showing separate [Pin] RLC circuits for I/Os.")
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Subckt 4 – Die Subckt 5 – Package 12341234 567567 8 9 10 POWER pins (4) GND pins (4) Signal pin A1 Signal pin A2 Buffer A1 Buffer A2 PU PD PU PD sig.subckt Die1P1G2Sig 1 2 3 4 5 6 7 8 9 10.subckt Pkg1P1G2Sig 1 2 3 4 5 6 7 8 12341234 Pads A1 VDD_pad A2 VSS_pad 56785678 Subckt 4, Die Subckt 5, Package 10
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Circuit 4 & 5 Connections, by pad_name, pin_name and signal_name (same [Pin] keyword as previous) [Die Supply Pads] VDD_pad VDD VSS_pad VSS [Begin Interconnect Model] … (circuit 4) 1 Pad_I/O pin_name A1 2 Pad_rail pad_name VDD_pad 3 Pad_I/O pin_name A2 4 Pad_rail pad_name VSS_pad 5 Puref pin_name A1 6 Buffer_I/O pin_name A1 7 Pdref pin_name A1 8 Puref pin_name A2 9 Buffer_I/O pin_name A2 10 Pdref pin_name A2 [End Interconnect Model].subckt Die1P1G2Sig 1 2 3 4 5 6 7 8 9 10.subckt Pkg1P1G2Sig 1 2 3 4 5 6 7 8 A1 P1 P2 P3 P4 G1 G2 G3 G4 A2 12341234 567567 8 9 10 PU(A1) PD(A1) A1 PU(A2) PD(A2) A2 12341234 56785678 [Begin Interconnect Model] … (circuit 5) 1 Pin_I/O pin_name A1 2 Pin_rail signal_name VDD 3 Pin_rail signal_name VSS 4 Pin_I/O pin_name A2 5 Pad_I/O pin_name A1 6 Pad_rail pad_name VDD_pad 7 Pad_I/O pad_name A2 8 Pad_rail pad_name VSS_pad [End Interconnect Model] Subckt 4 Subckt 5 11
![Circuit 4 & 5 Connections, by pad_name, pin_name and signal_name (same [Pin] keyword as previous) [Die Supply Pads] VDD_pad VDD VSS_pad VSS [Begin Interconnect Model] … (circuit 4) 1 Pad_I/O pin_name A1 2 Pad_rail pad_name VDD_pad 3 Pad_I/O pin_name A2 4 Pad_rail pad_name VSS_pad 5 Puref pin_name A1 6 Buffer_I/O pin_name A1 7 Pdref pin_name A1 8 Puref pin_name A2 9 Buffer_I/O pin_name A2 10 Pdref pin_name A2 [End Interconnect Model].subckt Die1P1G2Sig subckt Pkg1P1G2Sig A1 P1 P2 P3 P4 G1 G2 G3 G4 A PU(A1) PD(A1) A1 PU(A2) PD(A2) A [Begin Interconnect Model] … (circuit 5) 1 Pin_I/O pin_name A1 2 Pin_rail signal_name VDD 3 Pin_rail signal_name VSS 4 Pin_I/O pin_name A2 5 Pad_I/O pin_name A1 6 Pad_rail pad_name VDD_pad 7 Pad_I/O pad_name A2 8 Pad_rail pad_name VSS_pad [End Interconnect Model] Subckt 4 Subckt 5 11](http://images.slideplayer.com./32/9930258/slides/slide_11.jpg "Circuit 4 & 5 Connections, by pad_name, pin_name and signal_name (same [Pin] keyword as previous) [Die Supply Pads] VDD_pad VDD VSS_pad VSS [Begin Interconnect Model] … (circuit 4) 1 Pad_I/O pin_name A1 2 Pad_rail pad_name VDD_pad 3 Pad_I/O pin_name A2 4 Pad_rail pad_name VSS_pad 5 Puref pin_name A1 6 Buffer_I/O pin_name A1 7 Pdref pin_name A1 8 Puref pin_name A2 9 Buffer_I/O pin_name A2 10 Pdref pin_name A2 [End Interconnect Model].subckt Die1P1G2Sig subckt Pkg1P1G2Sig A1 P1 P2 P3 P4 G1 G2 G3 G4 A PU(A1) PD(A1) A1 PU(A2) PD(A2) A [Begin Interconnect Model] … (circuit 5) 1 Pin_I/O pin_name A1 2 Pin_rail signal_name VDD 3 Pin_rail signal_name VSS 4 Pin_I/O pin_name A2 5 Pad_I/O pin_name A1 6 Pad_rail pad_name VDD_pad 7 Pad_I/O pad_name A2 8 Pad_rail pad_name VSS_pad [End Interconnect Model] Subckt 4 Subckt 5 11")
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Subckt 6 – Package + Die, Two Power Distribution Circuits 123456123456 7 8 9 10 11 12 POWER pins (2) GND pins (2) Signal pin A1 Signal pin A2 Buffer A1 PU PD sig.subckt PkgDie1P1G2Sig 1 2 3 4 5 6 7 8 9 10 11 12 POWER pins (2) GND pins (2) Buffer A2 PU PD sig 12
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Subckt 6 Connections, I/O by pin_name, POWER/GND by signal_name and bus_label A1 P1 P2 P3 P4 A2 G1 G2 G3 G4 [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD1 POWER P2 VDD1 POWER P3 VDD2 POWER P4 VDD2 POWER G1 VSS1 GND G2 VSS1 GND G3 VSS2 GND G4 VSS2 GND 123456123456 7 8 9 10 11 12 [Begin Interconnect Model] … 1 Pin_I/O pin_name A1 2 Pin_rail signal_name VDD1 3 Pin_rail signal_name VDD2 4 Pin_I/O pin_name A2 5 Pin_rail signal_name VSS1 6 Pin_rail signal_name VSS2 7 Buffer_rail bus_label VDDbus1 8 Buffer_I/O pin_name A1 9 Buffer_rail bus_label VSSbus1 10 Buffer_rail bus_label VDDbus2 11 Buffer_I/O pin_name A2 12 Buffer_rail bus_label VSSbus2 [End Interconnect Model] PU(A1) PD(A1) A1 PU(A2) PD(A2) A2 [Pin Mapping] pulldown_ref pullup_ref A1 VSSbus1 VDDbus1 A2 VSSbus2 VDDbus2 P1 NC VDDbus1 P2 NC VDDbus1 P3 NC VDDbus2 P4 NC VDDbus2 G1 VSSbus1 NC G2 VSSbus1 NC G3 VSSbus2 NC G4 VSSbus2 NC 13
![Subckt 6 Connections, I/O by pin_name, POWER/GND by signal_name and bus_label A1 P1 P2 P3 P4 A2 G1 G2 G3 G4 [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD1 POWER P2 VDD1 POWER P3 VDD2 POWER P4 VDD2 POWER G1 VSS1 GND G2 VSS1 GND G3 VSS2 GND G4 VSS2 GND [Begin Interconnect Model] … 1 Pin_I/O pin_name A1 2 Pin_rail signal_name VDD1 3 Pin_rail signal_name VDD2 4 Pin_I/O pin_name A2 5 Pin_rail signal_name VSS1 6 Pin_rail signal_name VSS2 7 Buffer_rail bus_label VDDbus1 8 Buffer_I/O pin_name A1 9 Buffer_rail bus_label VSSbus1 10 Buffer_rail bus_label VDDbus2 11 Buffer_I/O pin_name A2 12 Buffer_rail bus_label VSSbus2 [End Interconnect Model] PU(A1) PD(A1) A1 PU(A2) PD(A2) A2 [Pin Mapping] pulldown_ref pullup_ref A1 VSSbus1 VDDbus1 A2 VSSbus2 VDDbus2 P1 NC VDDbus1 P2 NC VDDbus1 P3 NC VDDbus2 P4 NC VDDbus2 G1 VSSbus1 NC G2 VSSbus1 NC G3 VSSbus2 NC G4 VSSbus2 NC 13](http://images.slideplayer.com./32/9930258/slides/slide_13.jpg "Subckt 6 Connections, I/O by pin_name, POWER/GND by signal_name and bus_label A1 P1 P2 P3 P4 A2 G1 G2 G3 G4 [Pin] signal_name model_name A1 DQ1 DQ A2 DQ2 DQ P1 VDD1 POWER P2 VDD1 POWER P3 VDD2 POWER P4 VDD2 POWER G1 VSS1 GND G2 VSS1 GND G3 VSS2 GND G4 VSS2 GND [Begin Interconnect Model] … 1 Pin_I/O pin_name A1 2 Pin_rail signal_name VDD1 3 Pin_rail signal_name VDD2 4 Pin_I/O pin_name A2 5 Pin_rail signal_name VSS1 6 Pin_rail signal_name VSS2 7 Buffer_rail bus_label VDDbus1 8 Buffer_I/O pin_name A1 9 Buffer_rail bus_label VSSbus1 10 Buffer_rail bus_label VDDbus2 11 Buffer_I/O pin_name A2 12 Buffer_rail bus_label VSSbus2 [End Interconnect Model] PU(A1) PD(A1) A1 PU(A2) PD(A2) A2 [Pin Mapping] pulldown_ref pullup_ref A1 VSSbus1 VDDbus1 A2 VSSbus2 VDDbus2 P1 NC VDDbus1 P2 NC VDDbus1 P3 NC VDDbus2 P4 NC VDDbus2 G1 VSSbus1 NC G2 VSSbus1 NC G3 VSSbus2 NC G4 VSSbus2 NC 13")
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