1. THE A-TEAM MATHIVATHANI BARATHI MOHAN DINESH UDAYAKUMAR BHARGAV BHAT BHASKAR

4. CLIENT 1 SERVER 1 CLIENT 2 SERVER 2 SOFTWARE ROUTER HARDWAR E ROUTER

5. BUYER 1 COMPANY B CLIENT 1 CLIENT 2 SERVER 2 SOFTWARE ROUTER HARDWAR E ROUTER STOCK MARKET SCENARIO BUYER 2 COMPANY A SERVER 1

6. BUYER 1 COMPANY B STOCK MARKET SCENARIO BUYER 2 COMPANY A CUSTOM NETWORK PROCESSOR PAIRS TRADING ALGORITHM

7. MAC RxQ CPU RxQ MAC RxQ CPU RxQ MAC RxQ CPU RxQ MAC RxQ CPU RxQ Input Arbiter Output Port Lookup MAC TxQ CPU TxQ MAC TxQ CPU TxQ MAC TxQ CPU TxQ MAC TxQ CPU TxQ Output Queues Custom Network Processor Incoming Packets IMPLEMENTATION ON NETFPGA

8. Control Unit FIFO/DATA MEMORY PC ALU Ctrl Branch PC+1 Branch Address Jump Jump Address Thread Scheduler FALL THROUGH FIFO INSTRUCTION MEMORY 1 INSTRUCTION MEMORY 2 INSTRUCTION MEMORY 3 INSTRUCTION MEMORY 4 REGISTER FILE 1 REGISTER FILE 2 REGISTER FILE 3 REGISTER FILE 4 REG_SEL ALUSrcB MemToReg ALU INCOMING PACKETS FROM OUTPUT PORT LOOKUP OUT_FIFO Memory Ctrl Start_write Start_proc Start_read User Authentication Module Valid Invalid Scratch Mem CUSTOM NETWORK PROCESSOR

9. Invalid PASSKEY Look Up in_data Valid USER AUTHENTICATED MALICIOUS USER Header 0EA8CD517 USER AUTHENTICATION MODULE 0EA8CD517 0DC127131 Header FFFFFFFF

10. Control Unit PC ALU Ctrl Branch PC+1 Branch Address Jump Jump Address Thread Scheduler FALL THROUGH FIFO REG_SEL ALUSrcB MemToReg ALU INCOMING PACKETS FROM OUTPUT PORT LOOKUP OUT_FIFO Memory Ctrl Start_write Start_proc Start_read User Authentication Module Valid Invalid Packet Header Dst.Port Src.Port Length 0001 1000 0000000A 100 0010 1000 0000000A FIFO/Data Mem Scratch Mem INSTR 4 INSTR 3 INSTR 2 INSTR 1 n0 port addr n1 port addr n0 val n1 val

11. MAC RxQ CPU RxQ MAC RxQ CPU RxQ MAC RxQ CPU RxQ MAC RxQ CPU RxQ Input Arbiter Output Port Lookup MAC TxQ CPU TxQ MAC TxQ CPU TxQ MAC TxQ CPU TxQ MAC TxQ CPU TxQ Output Queues Custom Network Processor Incoming Packets IMPLEMENTATION ON NETFPGA

12. REFERENCE PLATFORM Mininet Acts as an instant virtual network. Allows to create custom topologies. Controller module programmed using Python scripts.

13. SOFTWARE ROUTER HOST 2 HOST 3 HOST O HOST 1 TOPOLOGY

14. Latency Comparison – Hardware Vs Software Routers Time in ms No of Bytes per packet

15. DateTasksStatus 6 th AprilMultithreaded ProcessorCompleted 13 th AprilAnalysis of packet contentsCompleted 20 th AprilSoftware Router DesignCompleted 27 th AprilMimicking Pairs Trading AlgorithmCompleted 27 th AprilImplementation of User AuthenticationIn Progress 27 th AprilImplementation of Rerouting mechanismIn Progress Analysis of achieved resultsYet to start