1. Week 14a, Fall 2005EE42/100, Prof. White1 Week 14a: Micro- and Nanotechnology 1.Some preliminaries: a.End of the propagation delay story b.“Silicon Run” (video) CMOS discussion – if time c.(Just for fun: “Hop On Board” -- Microlab safety video) – if time d.Energy Band View of Semiconductors if time -- shortened version of notes handed out earlier e. Some electronic application examples – if time 2.Micro- and Nanotechnology introduction 1.The sizes of things 2.Some micromachines 3.A bit about nanotech 3.What about radio?

2. Week 14a, Fall 2005EE42/100, Prof. White2 1a. Propagation delay in logic circuits

3. Week 14a, Fall 2005EE42/100, Prof. White3 D t t t t t Logic state DD DD DD 2D2D 2D2D 0 3D3D DD TIMING DIAGRAMS Show transitions of variables vs time A B C Note that becomes valid two gate delays after B&C switch, because the invert function takes one delay and the NAND function a second. No change at t = 3  D Note becomes valid one gate delay after B switches

4. Week 14a, Fall 2005EE42/100, Prof. White4 WHAT IS THE ORIGIN OF GATE DELAY? Logic gates are electronic circuits that process electrical signals Most common signal for logic variable: voltage Note that the specific voltage range for 0 or 1 depends on “logic family,” and in general decreases with logic generations Specific voltage ranges correspond to “0” or “1” Thus delay in voltage rise or fall (because of delay in charging internal capacitances) will translate to a delay in signal timing

5. Week 14a, Fall 2005EE42/100, Prof. White5 VOLTAGE WAVEFORMS (TIME FUNCTIONS) Inverter input is v IN (t), output is v OUT (t) inside a large system t V in (t)

6. Week 14a, Fall 2005EE42/100, Prof. White6 Approximation DD GATE DELAY (PROPAGATION DELAY) Define  as the delay required for the output voltage to reach 50% of its final value. In this example we will use 3V logic, so halfway point is 1.5V. Inverters are designed so that the gate delay is symmetrical (rise and fall) V in (t) t 1.5 V out (t) t 1.5 DD DD

7. Week 14a, Fall 2005EE42/100, Prof. White7 Example The gate delay is simply the charging of the capacitors at internal nodes. Oversimplified example using “ideal inverter, II ” and 5V logic swing 2.5 5 RC = 0.1ns so 0.069ns after v IN switches by 5V, Vx moves 2.5V t v IN 2.5 5 VxVx  D = 0.069ns v OUT II R C Vx RC = 0.1ns MODEL WHAT DETERMINES GATE DELAY?

8. Week 14a, Fall 2005EE42/100, Prof. White8 Controlled Switch Model of Inverter So if V IN is 2V then S N is closed and S P is open. Hence V OUT is zero. Input Output RNRN - + S P is closed if V IN < V DD RPRP - + + - + - V DD = 2V V SS = 0V SNSN SPSP S N is closed if V IN > V SS V IN V OUT But if V IN is 0V then S P is closed and S N is open. Hence V OUT is 2V.

9. Week 14a, Fall 2005EE42/100, Prof. White9 EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEED Computer architects would like each system clock cycle to have between 20 and 50 gate delays … use 35 for calculations Implication: if clock frequency = 500 MHz clock period = (5  10 8 s  1 )  1 Period = 2  10  9 s = 2 ns (nanoseconds) Gate delay must be  D = (1/35)  Period = (2 ns)/35 = 57 ps (picoseconds) How fast is this? Speed of light: c = 3  10 8 m/s Distance traveled in 57 ps is: C X  D = (3x10 8 m/s)(57x10 -12 ) = 17 x 10 -4 m = 1.7cm

10. Week 14a, Fall 2005EE42/100, Prof. White10 1d. Energy Band View of Semiconductors Conductors, semiconductors, insulators: Why is it that when individual atoms get close together to form a solid – such as copper, silicon, or quartz – they form materials that have a high, variable, or low ability to conduct current? Understand in terms of allowed, empty, and occupied electronic energy levels and electronic energy bands. Fig. 1 shows the calculated allowed energy levels for electrons (vertical axis) versus distance between atoms (horizontal axis) for materials like silicon.

11. Week 14a, Fall 2005EE42/100, Prof. White11 Fig. 1. Calculated energy levels in the diamond structure as a function of assumed atomic spacing at T = 0 o K. (From “Introduction to Semiconductor Physics”, Wiley, 1964)

12. Week 14a, Fall 2005EE42/100, Prof. White12 In Fig. 1, at right atoms are essentially isolated; at left atomic separations are just a few tenths of a nanometer, characteristic of atoms in a silicon crystal. If we start with N atoms of silicon at the right, which have 14 electrons each, there must be 14N allowed energy levels for the electrons. (You learned about this in physics in connection with the Bohr atom, the Pauli Exclusion principle, etc.) If the atoms are pushed together to form a solid chunk of silicon, the electrons of neighboring atoms will interact and the allowed energy levels will broaden into energy bands.

13. Week 14a, Fall 2005EE42/100, Prof. White13 When the “actual spacing” is reached, the quantum-mechanical calculation results are that: at lowest energies very narrow ranges of energy are allowed for inner electrons (these are core electrons, near the nuclei); a higher band of 4N allowed states exists that, at 0 o K, is filled with 4N electrons; then an energy gap, E G, appears with no allowed states (no electrons permitted!); and at highest energies a band of allowed states appears that is entirely empty at 0 o K. Can this crystal conduct electricity?

14. Week 14a, Fall 2005EE42/100, Prof. White14 NO, it cannot conductor electricity at 0 o K because that involves moving charges and therefore an increase of electron energy – but we have only two bands of states separated by a forbidden energy gap, E G. The (lower) valence band is entirely filled, and the (upper) conduction band states are entirely empty. To conduct electricity we need to have a band that has some filled states (some electrons!) and some empty states that can be occupied by electrons whose energies increase.

15. Week 14a, Fall 2005EE42/100, Prof. White15 A. Conductors such as aluminum and gold can conduct at low temperatures because the highest energy band is only partly filled – there are electrons and there are empty states they can move into when caused to move by an applied electric field. B. Silicon at 0K – can’t conduct because the highest band containing electrons is filled. C.Pure silicon at room temp. is slightly conductive since thermal energy can raise some electrons to the mostly empty conduction band. D.Silicon doped with donors (like P or As) can conduct (and Become n-type) better than pure silicon at room temp. since it doesn’t take much energy to free a valence electron so it can enter the conduction band. E.Silicon doped with acceptors (like B) can conduct (and become p-type) at room temp. since it doesn’t take much energy to free a valence electron and create a hole in the valence band. Metals, pure silicon at 0K and 300K, and doped silicon

16. Week 14a, Fall 2005EE42/100, Prof. White16 A. Metal B. Pure Si 0K C. Pure Si at 300K D. n-type Si E. p-type Si Conduction band Valence band Donor level Acceptor level Forbidden energy band (energy gap) +++ ---

17. Week 14a, Fall 2005EE42/100, Prof. White17 2. Micro- and Nanotechnology

18. Week 14a, Fall 2005EE42/100, Prof. White18 The Sizes of Things

19. Week 14a, Fall 2005EE42/100, Prof. White19 (Gordon) Moore’s Law

20. Week 14a, Fall 2005EE42/100, Prof. White20 Inkjet printer head: A thin-film heater behind each nozzle vaporizes the ink and ejects a droplet of ink

21. Week 14a, Fall 2005EE42/100, Prof. White21 Micro-guitar from Cornell University (the strings actually vibrate when plucked)

22. Week 14a, Fall 2005EE42/100, Prof. White22

23. Week 14a, Fall 2005EE42/100, Prof. White23 Early micromachine (with dead mite)

24. Week 14a, Fall 2005EE42/100, Prof. White24 Laser scanning micromachine with electrostatic motors, gears, and mirror

25. Week 14a, Fall 2005EE42/100, Prof. White25 Micromachine: Safety lock for nuclear bomb

26. Week 14a, Fall 2005EE42/100, Prof. White26 Digital Light Projector (Texas Instruments)

27. Week 14a, Fall 2005EE42/100, Prof. White27 16-micron-square tilting mirrors built over CMOS drive circuit

28. Week 14a, Fall 2005EE42/100, Prof. White28 Microstructures etched in Teflon -- useful in BioMEMS applications

29. Week 14a, Fall 2005EE42/100, Prof. White29 Nanotechnology Defining Dimension: Involves products and processes with significant features 100 nanometers and smaller. (To be listed in Merrill Lynch nanotechnology index, a company must indicate in a public document that nanotechnology initiatives are a significant component of their business strategy) Significant because of unusual properties: Mechanical – very strong; new devices (e.g., motor) Physics – new phenomena (e.g., metallic or semiconducting) Chemical – Reactivity, tiny hollow structures (e.g., can carry drugs into body)

30. Week 14a, Fall 2005EE42/100, Prof. White30 Nanotech examples Uses demonstrated: Electrostaically driven nanomotor (Alex Zettl, UCB Physics) Field effect transistors and logic devices (Ph. Avouris, Nano-Letters 16 Aug. 2001) – NOR gate, flip-flop memory cell, ring oscillator) Sensors (Nanometrix Co.) – hydrogen sensing by palladium- coated silicon nanotube operating as an FET Liquid repellent cloth Cautions (research needed): “Gray goo” – if nanotech replicating structures are made they could take over the Earth Nanostructures can pass through/around cells in the body Nanostructures may clump in liquids and have limited uses in environmental remediation, drug delivery

31. Week 14a, Fall 2005EE42/100, Prof. White31 C 60 -- Buckeyball

32. Week 14a, Fall 2005EE42/100, Prof. White32 Nano structures Carbon nanotube field-effect transistor

33. Week 14a, Fall 2005EE42/100, Prof. White33 3. What About Radio?

34. Week 14a, Fall 2005EE42/100, Prof. White34 Amplitude Modulation (AM) Radio

35. Week 14a, Fall 2005EE42/100, Prof. White35 Frequency Modulation (FM) Radio

36. Week 14a, Fall 2005EE42/100, Prof. White36 Crystal Set AM Radio Receiver – no batteries!