1. Technical University Tallinn, ESTONIA 1 Raimund Ubar TTÜ raiub@pld.ttu.ee www.ttu.ee/ˇraiub/ Tallinn, 21. mai 2003 Hästitestitavad ja isetestivad digitaalsüsteemid

2. Technical University Tallinn, ESTONIA 2 OUTLINE Basics of Testability Design for Testability Built-In Self-Test Pseudorandom test generation with LFSR Response compression methods, Signature Analyzer BIST Architectures Hybrid BIST

3. Technical University Tallinn, ESTONIA 3 Design for Testability The problem is - QUALITY: Quality policy Yield (Y) P,n Defect level (DL) P a Design for testability Testing P - probability of a defect n - number of defects P a - probability of accepting a bad product - probability of producing a good product

4. Technical University Tallinn, ESTONIA 4 Design for Testability Tradeoffs: DL   T  Testability   DL   T  DFT: Resynthesis or adding extra hardware Logic complexity  Area  Number of I/O  Performance  Power consumption  Yield  Economic tradeoff: C (Design + Test) < C (Design) + C (Test)

5. Technical University Tallinn, ESTONIA 5 Testability Measures Evaluation of testability:  Controllability  C 0 (i)  C 1 (j)  Observability  O Y (k)  O Z (k)  Testability 1 2 20 & & 1 2 1 x Defect Probability of detecting 1/2 60 1 2 20 & 1 2 1 i k j Y Z Controllability for 1 needed

6. Technical University Tallinn, ESTONIA 6 Ad Hoc Design for Testability Techniques Redundancy should be avoided: If a redundant fault occurs, it may invalidate some test for nonredundant faults Redundant faults cause difficulty in calculating fault coverage Much test generation time can be spent in trying to generate a test for a redundant fault Redundancy intentionally added: To eliminate hazards in combinational circuits To achieve high reliability (using error detecting circuits) Logical redundancy: 1 & & & 1 1 0101 1010 0101 1 1 Hazard control circuitry: Redundant AND-gate Fault  0 not testable  0 0

7. Technical University Tallinn, ESTONIA 7 Ad Hoc Design for Testability Techniques Fault redundancy: Error control circuitry: Decoder   1 1 E = 1 if decoder is fault-free Fault  1 not testable E Testable error control circuitry: Decoder   1 1 T  0 - normal working mode T = 1 - testing mode E T

8. Technical University Tallinn, ESTONIA 8 OUTLINE Basics of Testability Design for Testability Built-In Self-Test Pseudorandom test generation with LFSR Response compression methods, Signature Analyzer BIST Architectures Hybrid BIST

9. Technical University Tallinn, ESTONIA 9 Testability of Design Types General important relationships:  T (Sequential logic) < T (Combinational logic) Solutions: Scan-Path design strategy  T (Control logic) < T (Data path) Solutions: Data-Flow design, Scan-Path design strategies  T (Random logic) < T (Structured logic) Solutions: Bus-oriented design, Core-oriented design  T (Asynchronous design) < T (Synchronous design)

10. Technical University Tallinn, ESTONIA 10 Testability Estimations for Circuit Types Circuits less controllable Decoders Circuits with feedback Counters Clock generators Oscillators Self-timing circuits Self-resetting circuits Circuits less observable Circuits with feedback Embedded –RAMs –ROMs –PLAs Error-checking circuits Circuits with redundant nodes

11. Technical University Tallinn, ESTONIA 11 Testability Measures Signal probabilities as controllabilities: & & & a c y & b 1 2 3 2121 2 2323 Parker - McCluskey algorithm: p y = p c p 2 = (1- p a p b ) p 2 = = (1 – (1- p 1 p 2 ) (1- p 2 p 3 )) p 2 = = p 1 p 2 2 + p 2 2 p 3 - p 1 p 2 3 p 3 = = p 1 p 2 + p 2 p 3 - p 1 p 2 p 3 = 0,38 Calculation gate by gate: p a = 1 – p 1 p 2 = 0,75, p b = 0,75, p c = 0,4375, p y = 0,22 For all inputs: p k = 1/2

12. Technical University Tallinn, ESTONIA 12 Ad Hoc Design for Testability Techniques Multiplexing monitor points: OUT 0 1 2 n -1 x0x0 xnxn x1x1 MUX To reduce the number of output pins for observing monitor points, multiplexer can be used: 2 n observation points are replaced by a single output and n inputs to address a selected observation point Disadvantage: only one observation point can be observed at a time

13. Technical University Tallinn, ESTONIA 13 Ad Hoc Design for Testability Techniques Demultiplexer for implementing control points: 0 1 N DMUX To reduce the number of input pins for controlling testpoints, demultiplexer and a latch register can be used. N clock times are required between test vectors to set up the proper control values x CP1 CP2 CPN N = 2 n x1x1 x2x2 xNxN

14. Technical University Tallinn, ESTONIA 14 Time-sharing of outputs for monitoring To reduce the number of output pins for observing monitor points, time- sharing of working outputs can be introduced: no additional outputs are needed To reduce the number of inputs, again counter or shift register can be used Disadvantage: only one observation point can be observed at a time Original circuit MUX

15. Technical University Tallinn, ESTONIA 15 Time-sharing of inputs for controlling 0 1 N DMUX CP1 CP2 CPN To reduce the number of input pins for controlling test points, time-sharing of working inputs can be introduced. To reduce the number of inputs for driving the address lines of demultiplexer, counter or shift register can be used Normal input lines

16. Technical University Tallinn, ESTONIA 16 Scan-Path Design Combinational circuit IN OUT R Scan-IN Scan-OUT 1 & & q q’ Scan-IN T TD C Scan-OUT q q’ The complexity of testing is a function of the number of feedback loops and their length The longer a feedback loop, the more clock cycles are needed to initialize and sensitize patterns Scan-register is a aregister with both shift and parallel-load capability T = 0 - normal working mode T = 1 - scan mode Normal mode : flip-flops are connected to the combinational circuit Test mode: flip-flops are disconnected from the combinational circuit and connected to each other to form a shift register

17. Technical University Tallinn, ESTONIA 17 Scan-Path Design and Testability OUT MUX DMUX IN SCAN OUT SCAN IN Two possibilities for improving controllability/observability

18. Technical University Tallinn, ESTONIA 18 Built-In Self-Test Motivations for BIST: –Need for a cost-efficient testing –Doubts about the stuck-at fault model –Increasing difficulties with TPG (Test Pattern Generation) –Growing volume of test pattern data –Cost of ATE (Automatic Test Equipment) –Test application time –Gap between tester and UUT (Unit Under Test) speeds Drawbacks of BIST: –Additional pins and silicon area needed –Decreased reliability due to increased silicon area –Performance impact due to additional circuitry –Additional design time and cost

19. Technical University Tallinn, ESTONIA 19 BIST Techniques BIST techniques are classified: –on-line BIST - includes concurrent and nonconcurrent techniques –off-line BIST - includes functional and structural approaches On-line BIST - testing occurs during normal functional operation –Concurrent on-line BIST - testing occurs simultaneously with normal operation mode, usually coding techniques or duplication and comparison are used –Nonconcurrent on-line BIST - testing is carried out while a system is in an idle state, often by executing diagnostic software or firmware routines Off-line BIST - system is not in its normal working mode, usually –on-chip test generators and output response analyzers or microdiagnostic routines –Functional off-line BIST is based on a functional description of the Component Under Test (CUT) and uses functional high-level fault models –Structural off-line BIST is based on the structure of the CUT and uses structural fault models (e.g. SAF)

20. Technical University Tallinn, ESTONIA 20 Built-In Self-Test System-on-Chip testing Test architecture components: Test pattern source & sink Test Access Mechanism Core test wrapper Solutions: Off-chip solution –need for external ATE Combined solution –mostly on-chip, ATE needed for control On-chip solution –BIST

21. Technical University Tallinn, ESTONIA 21 Built-In Self-Test BIST components: –Test pattern generator (TPG) –Test response analyzer (TRA) TPG & TRA are usually implemented as linear feedback shift registers (LFSR) Two widespread schemes: –test-per-scan –test-per-clock

22. Technical University Tallinn, ESTONIA 22 Built-In Self-Test Embedded tester for testing multiple cores

23. Technical University Tallinn, ESTONIA 23 Pseudorandom Test Generation LFSR – Linear Feedback Shift Register: 1xx2x2 x3x3 x4x4 x2x2 x 1 x4x4 x3x3 Polynomial: P(x) = 1 + x 3 + x 4 Standard LFSR Modular LFSR

24. Technical University Tallinn, ESTONIA 24 Built-In Self-Test Problems: Very long test application time Low fault coverage Area overhead Additional delay Possible solutions Combining pseudorandom test with deterministic test –Multiple seed –Bit flipping Hybrid BIST

25. Technical University Tallinn, ESTONIA 25 BIST: Weighted pseudorandom test Hardware implementation of weight generator LFSR && & MUX Weight select Desired weighted value Scan-IN 1/2 1/41/8 1/16

26. Technical University Tallinn, ESTONIA 26 OUTLINE Basics of Testability Design for Testability Built-In Self-Test Pseudorandom test generation with LFSR Response compression methods, Signature Analyzer BIST Architectures Hybrid BIST

27. Technical University Tallinn, ESTONIA 27 BIST: Response Compression 1. Parity checking UUT Test T riri P i-1 2. One counting UUT Test riri Counter 3. Zero counting

28. Technical University Tallinn, ESTONIA 28 Signature Analyser 1xx2x2 x3x3 x4x4 x2x2 x 1 x4x4 x3x3 Polynomial: P(x) = 1 + x 3 + x 4 Standard LFSR Modular LFSR UUT Response string Response in compacted by LFSR The content of LFSR after test is called signature

29. Technical University Tallinn, ESTONIA 29 Signature Analysis In signature testing we mean the use of CRC encoding as the data compressor G(x) and the use of the remainder R(x) as the signature of the test response string P(x) from the UUT Signature is the CRC code word Example: 1 0 1 = Q(x) = x 2 + 1 1 0 1 0 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 = R(x) = x 3 + x 2 + 1 P(x) G(x) Signature

30. Technical University Tallinn, ESTONIA 30 Signature Analysis 1 0 1 1 0 1 0 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 = R(x) = x 3 + x 2 + 1 P(x) G(x) Signature The division process can be mechanized using LFSR The divisor polynomial G(x) is defined by the feedback connections Shift creates x 5 which is replaced by x 5 = x 3 + x + 1 x0x0 x1x1 x2x2 x3x3 x4x4 IN IN: 01 010001 Shifted into LFSR x5x5

31. Technical University Tallinn, ESTONIA 31 Signature Analysis Aliasing: UUT Response SA L N L - test length N - number of stages in Signature Analyzer All possible responses All possible signatures Faulty response Correct response

32. Technical University Tallinn, ESTONIA 32 Signature Analysis Aliasing: UUT Response SA L N L - test length N - number of stages in Signature Analyzer - number of different possible responses No aliasing is possible for those strings with L - N leading zeros since they are represented by polynomials of degree N - 1 that are not divisible by characteristic polynomial of LFSR. There are such strings Probability of aliasing:

33. Technical University Tallinn, ESTONIA 33 LFSR: Signature Analyser & Test Generator 1 xx2x2 x3x3 x4x4 LFSR UUT Response string for Signature Analysis Test Pattern (when generating tests) Signature (when analyzing test responses) FF

34. Technical University Tallinn, ESTONIA 34 LFSR: Signature Analyser x2x2 x 1 x4x4 x3x3 Parallel Signature Analyzer: UUT x2x2 x 1 x4x4 x3x3

35. Technical University Tallinn, ESTONIA 35 Signature Analysis Signature calculating for multiple outputs: LFSR - Test Pattern Generator Combinational circuit LFSR - Signature analyzer Multiplexer LFSR - Test Pattern Generator Combinational circuit LFSR - Signature analyzer Multiplexer

36. Technical University Tallinn, ESTONIA 36 OUTLINE Basics of Testability Design for Testability Built-In Self-Test Pseudorandom test generation with LFSR Response compression methods, Signature Analyzer BIST Architectures Hybrid BIST

37. Technical University Tallinn, ESTONIA 37 BIST Components BIST components: –Test pattern generator (TPG) –Test response analyzer (TRA) –BIST controller A part of a system (hardcore) must be operational to execute a self-test At minimum the hardcore usually includes power, ground, and clock circuitry Hardcore should be tested by –external test equipment or –it should be designed self- testable by using various forms of redundancy General Architecture of BIST

38. Technical University Tallinn, ESTONIA 38 BIST: Test per Scan Assumes existing scan architecture Drawback: –Long test application time Initial test set: T1: 1100 T2: 1010 T3: 0101 T4: 1001 Test application: 1100 T 1010 T 0101T 1001 T Number of clocks = 4 x 4 + 4 = 20

39. Technical University Tallinn, ESTONIA 39 BIST: Test per Clock Initial test set: T1: 1100 T2: 1010 T3: 0101 T4: 1001 Test application: 1 10 0 1 0 1 0 01 01 1001 T 1 T 4 T 3 T 2 Number of clocks = 10 Combinational Circuit Under Test Scan-Path Register

40. Technical University Tallinn, ESTONIA 40 BIST Architectures Test per Clock: BILBO - Built- In Logic Block Observer: CSTP - Circular Self-Test Path: LFSR - Test Pattern Generator Combinational circuit LFSR - Signature analyzer LFSR - Test Pattern Generator & Signature analyser Combinational circuit

41. Technical University Tallinn, ESTONIA 41 BILBO Working modes: B1 B2 0 0Reset 0 1 Normal mode 1 0 Scan mode 1 1 Test mode Testing modes: CC1: LFSR 1 - TPG LFSR 2 - SA CC2:LFSR 2 - TPG LFSR 1 - SA LFSR 1 CC1 LFSR 2 CC2 B1 B2 B1 B2

42. Technical University Tallinn, ESTONIA 42 Circular Self-Test Circuit Under Test FF

43. Technical University Tallinn, ESTONIA 43 Circular Self-Test Path CSTP CC R R

44. Technical University Tallinn, ESTONIA 44 BIST Architectures Test Pattern Generator MISR R1 CC1... STUMPS: Self-Testing Unit Using MISR and Parallel Shift Register Sequence Generator LOCST: LSSD On-Chip Self-Test Rn CCn Error Test Controller SISO TPGSA CUT BS Scan Path

45. Technical University Tallinn, ESTONIA 45 OUTLINE Basics of Testability Design for Testability Built-In Self-Test Pseudorandom test generation with LFSR Response compression methods, Signature Analyzer BIST Architectures Hybrid BIST

46. Technical University Tallinn, ESTONIA 46 Store-and-Generate test architecture ROM contains test patterns for hard-to-test faults Each pattern P k in ROM serves as an initial state of the LFSR for test pattern generation (TPG) Counter 1 counts the number of pseudorandom patterns generated starting from P k After finishing the cycle for Counter 2 is incremented for reading the next pattern P k+1 ROMTPGUUT ADR Counter 2Counter 1 RD CL

47. Technical University Tallinn, ESTONIA 47 Hybrid Built-In Self-Test Hybrid test set contains a limited number of pseudorandom and deterministic vectors Pseudorandom test vectors can be generated either by hardware or by software Pseudorandom test is improved by a stored test set which is specially generated to shorten the on-line pseudorandom test cycle and to target the random resistant faults The problem is to find a trade-off between the on-line generated pseudorandom test and the stored test

48. Technical University Tallinn, ESTONIA 48 Optimization of Hybrid BIST Cost curves for BIST: Total Cost C TOTAL C Cost of pseudorandom test patterns C GEN Number of remaining faults after applying k pseudorandom test patterns r NOT (k) Cost of stored test C MEM L L OPT

49. Technical University Tallinn, ESTONIA 49 Hybrid BIST for Multiple Cores Embedded tester for testing multiple cores

50. Technical University Tallinn, ESTONIA 50 Hybrid BIST for Multiple Cores

51. Technical University Tallinn, ESTONIA 51 Optimized Multi-Core Hybrid BIST Pseudorandom test is carried out in parallel, deterministic test - sequentially

52. Technical University Tallinn, ESTONIA 52 Software Based BIST To reduce the hardware overhead cost in the BIST applications the hardware LFSR can be replaced by software, which is especially attractive to test SoCs, because of the availability of computing resources directly in the system (a typical SoC usually contains at least one processor core) Software based test generation: The TPG software is the same for all cores and is stored as a single copy All characteristics of the LFSR are specific to each core and stored in the ROM They will be loaded upon request. For each additional core, only the BIST characteristics for this core have to be stored

53. Technical University Tallinn, ESTONIA 53 Broadcasting Test Patterns in BIST Concept of test pattern sharing via novel scan structure – to reduce the test application time:... CUT 1 CUT 2... CUT 1 CUT 2 Traditional single scan design Broadcast test architecture While one module is tested by its test patterns, the same test patterns can be applied simultaneously to other modules in the manner of pseudorandom testing

54. Technical University Tallinn, ESTONIA 54 IEEE P1500 standard for core test The two most important components of the P1500 standard are –Core test language (CTL) and –Scalable core test architecture The following components are generally required to test embedded cores –Source for application of test stimuli and a sink for observing the responces –Test Access Mechanisms (TAM) to move the test data from the source to the core inputs and from the core outputs to the sink –Wrapper around the embedded core

55. Technical University Tallinn, ESTONIA 55 IEEE P1500 standard for core test

56. Technical University Tallinn, ESTONIA 56 Conclusions Scan design has been the backbone of DFT in the industry about three decade – the most popular DFT technique Recent variants: partial and boundary scan Penalties 10-15% in area overhead and 5% in speed are justified by the high quality of devices obtained in a short design time With properly designed BIST, the cost of added test HW will be more than balanced by the benefits in terms of –Reliability, and –Reduced maintenance cost The savings from BIST include –Reduced test generation effort at all levels –Reduced test effort at chip through system levels –Improved system-level maintenance and repair, and –Improved component repair