1. WCCI, Vancouver, Canada July 20, 2006 Level Compaction in Quantum Circuits D. Maslov - University of Waterloo, Canada G. W. Dueck - University of New Brunswick, Canada

2. WCCI, Vancouver, Canada July 20, 2006 Outline - Background - The templates (properties, definition) - Using templates for level compaction - Example - Results page 1/14

3. WCCI, Vancouver, Canada July 20, 2006 Background page 2/14 A quantum circuit is composed of gates arranged in a cascade: … In an n-bit quantum computation each gate is a unitary matrix.

4. WCCI, Vancouver, Canada July 20, 2006 Background page 3/14 NOT CNOT (Feynman) InOut 01 10 InOut 0 0 1 1 01 1 0 Some quantum gates

5. WCCI, Vancouver, Canada July 20, 2006 Background page 4/14 V Iff control value is 1, the target is changed according to. In practice, controlled-V gates are used w/Boolean controls. InOut 0 0 1 1 01 v0 1 1 v1 InOut 0 v0 0 v1 1 v01 1 v11 0 and

6. WCCI, Vancouver, Canada July 20, 2006 Background page 5/14 V+V+ Controlled-V+ is the inverse of controlled- V. - Set of gates: NOT, CNOT, controlled-V and controlled-V+ is complete. - Set of gates NOT and controlled-V is complete. - Controlled-V is complete on its own. With regards to synthesizing quantum Boolean functions and with the addition of a constant line:

7. WCCI, Vancouver, Canada July 20, 2006 The Templates: Definition Observation 1. If one has a circuit equality then the gates satisfy the equation Observation 3. If, then Observation 2. For each circuit and for any parameter p,. page 6/14

8. WCCI, Vancouver, Canada July 20, 2006 The Templates: Definition A size m template is a cascade of m gates that realizes the identity function. Any template T of size m should be independent of smaller size templates, i.e. application of smaller templates does not decrease the number of gates in T or make it equal to another template. Given G 0 G 1 …G m-1, a template of size m, its application for parameter p, is: - for page 7/14

9. WCCI, Vancouver, Canada July 20, 2006 The Templates: Definition A B C D E F G Example. Template ABCDEFG. p=4. Starting gate B. Direction: backward. B -1 B A -1 A G -1 G F -1 F C C D D E E page 8/14

10. WCCI, Vancouver, Canada July 20, 2006 Quantum Gate Templates Gate-inverse rule. Moving rule. Gate G 1 with control c 1 and target t 1 passes gate G 2 with c 2, t 2 iff Other templates: page 9/14

11. WCCI, Vancouver, Canada July 20, 2006 Level Compaction The non intersecting gates may be applied in parallel. Form a level by: - put the leftmost gate in the level; LEVEL CIRCUIT page 10/14

12. WCCI, Vancouver, Canada July 20, 2006 Level Compaction The non intersecting gates may be applied in parallel. Form a level by: LEVEL CIRCUIT - find a gate that can be put in a level and moves to the left of the circuit; page 10/14

13. WCCI, Vancouver, Canada July 20, 2006 Level Compaction The non intersecting gates may be applied in parallel. Form a level by: LEVEL CIRCUIT - if a size 2m template applies w/parameter m to a non- movable or non-arrangable gate, apply it and see what happens. page 10/14

14. WCCI, Vancouver, Canada July 20, 2006 Level Compaction V V+V+V+V+ V Levels: 012Can there be less than 10 levels? page 11/14

15. WCCI, Vancouver, Canada July 20, 2006 Level Compaction V+V+ V+V+ Levels: 2Can there be less than 10 levels? page 11/14

16. WCCI, Vancouver, Canada July 20, 2006 Level Compaction V+V+V+V+ Levels: 2 V+V+ V+V+ Can there be less than 10 levels? page 11/14

17. WCCI, Vancouver, Canada July 20, 2006 Level Compaction V+V+ Levels: 2 V+V+ V+V+ V+V+ Can there be less than 10 levels? page 11/14

18. WCCI, Vancouver, Canada July 20, 2006 Level Compaction Levels: 2 V+V+ V+V+ 348Can there be less than 10 levels? page 11/14

19. WCCI, Vancouver, Canada July 20, 2006 Level Compaction Levels: 8 page 11/14

20. WCCI, Vancouver, Canada July 20, 2006 Results R. V. Meter and K. M. Itoh. Fast quantum modular exponentiation. Physical Review A, 71(052320), May 2005. NameSizeGCLvlsOptimized GC Optimized Lvls Time (sec) Fig. 210604734200.07 Fig. 415704458230.21 Fig. 53016837112210.301 page 12/14

21. WCCI, Vancouver, Canada July 20, 2006 Results T. G. Draper, S. A. Kutin, E. M. Rains, and K. M. Svore. A logarithmic-depth quantum carry-lookahead adder. quant-ph/0406142, June 2004. NameSizeGCLvlsOptimized GC Optimized Lvls Time (sec) Fig. 53536886303531.883 Fig. 62417249110270.341 Fig. 726337101287611.903 page 13/14

22. WCCI, Vancouver, Canada July 20, 2006 Acknowledgements page 14/14 Natural Sciences and Engineering Research Council (NSERC), Canada

23. WCCI, Vancouver, Canada July 20, 2006 END Thank you for your attention!