1. Global Trigger, Global Muon Trigger H. Bergauer, Ch. Deldicque, J. Erö, A. Jeitler, K. Kastner, S. Kostner, A. Nentchev, B. Neuherz, N. Neumeister, M. Padrta, P. Porth, H. Rohringer, H. Sakulin, J. Strauss, A. Taurok, C.-E. Wulz Semi-Annual Review, CPT Week CERN, 5 May 2003 presented by Claudia-Elisabeth Wulz

2. Semi-Annual Review, May 2003 C.-E. Wulz2 Slides from Hannes Sakulin Global Muon Trigger

3. Semi-Annual Review, May 2003 C.-E. Wulz3 Global Muon Trigger Overview Output: 8 bit , 6 bit , 5 bit p T, 2 bits charge/synch, 3 bit quality, 1 bit MIP, 1 bit Isolation Inputs: 8 bit , 6 bit , 5 bit p T, 2 bits charge, 3 bit quality, 1 bit halo/eta fine-coarse Best 4  4  RPC brl 4  DT 4  CSC 4  RPC fwd 252 MIP bits 252 Quiet bits NEW

4. Semi-Annual Review, May 2003 C.-E. Wulz4 GMT Hardware Status  GMT consists of  3 pipeline synchronizing boards (PSBs)… prototype available  1 GMT logic board… logic design completed  All boards housed in GT crate & rack … see GT talk  FPGA design for GMT logic board in progress  Input FPGA (4x) … logic design completed  GMT logic FPGA (2x) … logic design completed  MIP and ISO assignment unit (2x) … FPGA firmware completed  Sorter FPGA (1x) … logic design completed  VME interface & read-out-processor  Milestones (unchanged since April 2002)  Dec 2002: logic design completed… completed  Dec 2003: FPGA design done… progress as planned  Jun 2004: GMT available  Oct 2004: GMT tested

5. Semi-Annual Review, May 2003 C.-E. Wulz5 GMT Progress in Last 6 Months  Improved functionality  Additional cancel-out units in overlap region (DT-fwdRPC, CSC-brlRPC)  Ghosting reduced below 0.1 % in 0.9 < |  | < 1.15  More robust w.r.t. shifts of RPC vs. DT/CSC  -boundary  Improved p T -assignment for matched pairs  Minimum p T method used in most regions  powerful rate reduction  In regions where minimum-p T decreases plateau efficiency  select p T by rank  Development of tools  Software for generation of look-up-table contents  In MIP/ISO assignment FPGA: 4 types of LUTs x 16 instances per chip  Software for generic handling of look-up-tables with automatic generation of all files for implementation of Xilinx firmware  Generation of test files from ORCA & VHDL test bench  Development of FPGA firmware  MIP & ISO assignment FPGA barrel done & verified against ORCA

6. Semi-Annual Review, May 2003 C.-E. Wulz6 Generic Handling of GMT LUTs C++ L1MuGMTLUT Class L1MuGMTLUT inputs, outputs, instances, contents Lookup(), Load(), Save() WriteVHDL() WriteHTML() virtual AlternateLookup() GenerateFromAlternate()... LUT master file complete description of LUT: I/O definition, list of instances default contents (for each incarnation) VHDL wrapper COE memory contents XCO DPM RAM definition XILINX Core Generator MIF memory contents VHDL simulation models EDIF netlists Behavioral Simulation FPGA Synthesis & Implementation C++ Class WriteVHDL() Load() Save().cc,.h easy access HTML display WriteHTML() MakeSubClass()

7. Semi-Annual Review, May 2003 C.-E. Wulz7 LUT2HW tool LUT Generation Appl. ORCA Generic Handling of GMT Look-Up-Tables LUT generation - Use in ORCA - Generation of files for firmware VHDL wrapper COE memory contents XCO DPM RAM definition Lookup() 1. Derive a C++ child class 2. Implement LUT functionality in derived AlternativeLookup() 3. Call GenerateFromAlternative() 4. Call Save() (One for each type of LUT in the GMT) L1MuGMTLUT inputs, outputs, instances, contents Load(), Save() virtual AlternateLookup() GenerateFromAlternate()... L1MuGMTLUT inputs, outputs, instances, contents Load(), Save() virtual AlternateLookup() GenerateFromAlternate()... L1MuGMTLUT inputs, outputs, instances, contents Load(), Save() virtual AlternateLookup() GenerateFromAlternate()... L1MuGMT_XY_LUT inputs, outputs, instances, contents Load(), Save() virtual AlternateLookup() GenerateFromAlternate()... Load() WriteVHDL() (2) ORCA simulation to be implemented … (3) Batch generation of files for Xilinx firmware (1) Lookup-table generation child class LUT master file Save()

8. Semi-Annual Review, May 2003 C.-E. Wulz8 Firmware Test: Data Flow Cross-check of ORCA simulation with FPGA firmware & GMT board Single type of hardware test file for all chips and for GMT board –All GMT inputs & outputs –Intermediate results at various points in GMT –For easier debugging: human readable with automatically generated comments such as parameters in meaningful units So far tested MIP and ISO assignment FPGA (barrel) with several hundred single-muon events –Full agreement with ORCA ORCA DT CSC RPC Calo GMT GT HW Testfile (ASCII) digi GMT Inputs GMT Outputs intermediate results VHDL test bench (for single chip or entire GMT) Chip or entire GMT VHDL Behavioral / Gate Level stimuliOutput signals Intermediate signals hits

9. Semi-Annual Review, May 2003 C.-E. Wulz9 MIP and ISO Assignment FPGAs Xilinx XC2V3000  Chip Inputs/Outputs  8 muons 200  180 MIP/ISO bits 180  out (isISO, isMIP) 16  VME 36  total 432  Memories 18 kbit blocks  96 / 96 used GMT Logic Board

10. Semi-Annual Review, May 2003 C.-E. Wulz10 MIP and ISO Assignment FPGAs development of firmware Developed VHDL model Simulated behavioral model & cross-checked with ORCA Synthesized using Synplify 7.21 Implemented with Xilinx ISE 5.2 Simulated chip-level VHDL & cross-checked with ORCA  Pin assignment to be re-iterated when board is being routed Xilinx XC2V3000

11. Semi-Annual Review, May 2003 C.-E. Wulz11 Conclusions on Global Muon Trigger  Improvements of GMT algorithm  New additional overlap region cancel-out-units  Optimized merging of p T measurements  Development of tools  Software for generation of look-up-table contents  Software for handling of look-up-table and generation of HW files  Generation of test data from ORCA simulation  VHDL test bench  Development of FPGA firmware  MIP and ISO assignment chip (barrel) done & verified against ORCA  Progress towards milestones as planned

12. Semi-Annual Review, May 2003 C.-E. Wulz12 Global Trigger PSB (Pipeline Synchronizing Buffer)Input synchronization (7 boards including GMT) GTL (Global Trigger Logic) Logic calculation (1-2 boards) FDL (Final Decision Logic) L1A decision (1 board) TCS (Trigger Control System Modeule)Central Trigger Control (1 board) L1A (Level-1 Accept Module)Delivery of L1A (1 board) TIM (Timing Board)Timing (1 board) GTFE (Global Trigger Frontend) Readout (1 board)

13. Semi-Annual Review, May 2003 C.-E. Wulz13 GT Conversion Board VME interface 80MHz GTL+ signals Channel LinkRec +1.5V supply VME to GTL6U Channel Link signals CONV chips GTL-CONV is used only in the Prototype Crate

14. Semi-Annual Review, May 2003 C.-E. Wulz14 Crate for Prototype Global Trigger VME interface PSB GTL6U GTL_CONV

15. Semi-Annual Review, May 2003 C.-E. Wulz15 GTL-6U Prototype (right side) VME REC chips COND chips GTL+ signals 4x4 calo objects 4 muons Calculates 64 Trigger algorithms

16. Semi-Annual Review, May 2003 C.-E. Wulz16 Mezzanine Board (MEZZ896) bottom side top side 50 Ohm connectors XC2V2000-4FF896C BGA: 1mm pitch, track width=83  m MEZZ896 will be used in TCS-9U and FDL-9U

17. Semi-Annual Review, May 2003 C.-E. Wulz17 Layout of USC55 Counting Room Racks Lower Floor

18. Semi-Annual Review, May 2003 C.-E. Wulz18 GT Rack

19. Semi-Annual Review, May 2003 C.-E. Wulz19 Boards and Cables in GT 9U Crate

20. Semi-Annual Review, May 2003 C.-E. Wulz20 Global Trigger Status and Milestones May 2003 Milestones as of Nov. 2002 or updated Custom Backplane for VME 9U crate 4 6U Prototype: Channel Links...existsMS 03/02 –9U Backplane: 80MHz GTLp and Channel Links,...design in progressMS 03/03  09/03 PSB Input board (synchronisation, monitoring) 4 6 channel 6U Prototype: Channel Link receivers... board testedMS 03/02 –12 channel board: memories inside FPGAs...conceptual design MS 06/04 GTL Logic board: 4 Conversion board for prototype... board testedMS 03/02 –GTL-6U prototype: 20 channels …board largely testedMS 06/03 Signal transfer tested with test patterns -> ok XDAQ compatible test program in C++ exists Loading of conditions not tested yet (software under development) –GTL-9U board: 32 channels...conceptual design MS 11/04 4 , 4 isol. e/ , 4e/ , 4 central jets, 4 fwd jets, 4  -jets,  E T, E T mis, H T, 12 jet counts TIM Timing board … New: board produced, tests in progessMS 06/03 –6U size, TTCrx, clock and L1A distribution, also used by DTTF FDL-9U Final Decision board... design in progressMS 06/03  11/03 TCS-9U Central Trigger Control board... design in progressMS 04/03  09/03 GTFE-9U Readout board...conceptual designMS 12/03  03/04

21. Semi-Annual Review, May 2003 C.-E. Wulz21 Production, Full Chain and Slice Tests, Integration GTL-6U  produced, testing TIM-6U  produced, testing TCS-9U  09/03 BACK-9U  09/03 FDL-9U  11/03 System test (full chain) of 20-channel GT  06/04 GT system tests  6/05 Global Trigger PSB-9U  06/04 Integration of GT/GMT with DAQ  01/06 Slice tests performed in Vienna as boards become available. Installation and commissioning in USC55 planned in phase with other subsystems (GCT, regional muon trigger systems) during second half of 2005. GTFE  03/04 GTL-9U  11/04 Global Muon Trigger FPGA design  12/03 Board production  06/04 GMT system tests  01/05 Global Trigger PROTOTYPE BACK-6Uok PSB-6U ok GTL-CONVok GTL-6U Milestone 6/03 TIM-6U Milestone 6/03 Chain Test with GCT (July 2003)

22. Semi-Annual Review, May 2003 C.-E. Wulz22 GT and GMT Manpower  Physicists A. Taurok (Project engineer), C.-E. Wulz (GT coordinator) H. Sakulin (logic and hardware design of GMT, simulation, on-line software) J. Strauss (on-line software) A. Jeitler (40%), P. Porth (60%), H. Rohringer (simulation) N. Neumeister (simulation, mainly working in PRS)  Technicians (shared with DTTF) H. Bergauer (60%), M. Padrta, K. Kastner - in Vienna Ch. Deldicque - at CERN  Students S. Kostner (20%), new: B. Neuherz (50%) (on-line software, hardware) New: A. Nentchev (50%) (on-line software)

23. Semi-Annual Review, May 2003 C.-E. Wulz23 Conclusions on Global Trigger  Boards  PSB-6U, BACK-6U, GTL-6U, GTL-CONV, TIM exist  TCS-9U, FDL-9U are being finalized  GTFE, GTL-9U foreseen in 2004, L1A depends on TTCci  Software production  XDAQ compatible software under development  CVI-based set-up program being changed to C++  Integration with calorimeter trigger to be tested soon  July 2003

24. Semi-Annual Review, May 2003 C.-E. Wulz24 URL’s This talk can be found at: http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalTrigger/trans/ wulz_CPT_may2003.ppt The GMT part of this talk can be found at: http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger/trans/ GMT-CPTWeek5May2003.pdf Detailed information about the Global Trigger and the Global Muon Trigger is available on the HEPHY Vienna web sites: http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalTrigger http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger