1. Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 4: September 12, 2012 Transistor Introduction (first order)

2. Today First order model There are always Rs and Cs Penn ESE370 Fall2012 -- DeHon 2

3. Previously Quasi-Static – inputs transition, circuit responds, and settles –Dynamic transition to roughly static states DC/Steady-State –Ignore the capacitors Zeroth-order allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits Penn ESE370 Fall2012 -- DeHon 3

4. Zero-th Order MOSFET Ideal Switch Vgs > Vth  conducts Vgs < Vth  does not conduct Vth – threshold voltage Gate draws no current from input –Loads input capacitively Penn ESE370 Fall2012 -- DeHon 4

5. Zero-th Order MOSFET Penn ESE370 Fall2012 -- DeHon 5 I DS

6. First Order Model Switch –Loads gate input capacitively C g –Has finite drive strength R on Penn ESE370 Fall2012 -- DeHon 6

7. Gate Output Assume this is equivalent circuit for gate output state Penn ESE370 Fall2012 -- DeHon 7

8. Gate Output Load What is Vout if gate is unloaded? Penn ESE370 Fall2012 -- DeHon 8

9. Gate Output Load What happens to Vout when add a load? Penn ESE370 Fall2012 -- DeHon 9

10. Resistive Load What happens when load is resistance? Penn ESE370 Fall2012 -- DeHon 10

11. Resistive Load If loaded resistively, and resistive load is too strong (resistance too low) Cause output voltage to drop Penn ESE370 Fall2012 -- DeHon 11

12. Capacitive Load What happens when load is capacitance? Penn ESE370 Fall2012 -- DeHon 12

13. Capacitive Load Capacitive load does not change the steady-state output voltage Will effect the delay (settling time) Penn ESE370 Fall2012 -- DeHon 13

14. First Order Model Switch –Loads gate input capacitively Draw no current Does not impact steady-state voltage Impacts Delay –Has finite drive strength Could form voltage divider with resistive load Impacts Delay Penn ESE370 Fall2012 -- DeHon 14

15. First Order Model (vs. Vds) Penn ESE370 Fall2012 -- DeHon 15

16. First Order Model (vs. Vgs) Penn ESE370 Fall2012 -- DeHon 16

17. Refine to First Order Penn ESE370 Fall2012 -- DeHon 17

18. Zero-th Order Tells us how switches set (Vin=0) Penn ESE370 Fall2012 -- DeHon 18 How are switches set in this case?

19. Zero-th Order Tells us how switches set (Vin=0) Penn ESE370 Fall2012 -- DeHon 19 V2=Vdd Vout=0

20. Zero-th Order Tells us how switches set (Vin=0) Penn ESE370 Fall2012 -- DeHon 20 V2=Vdd Vout=0

21. Zero-th Order Tells us how switches set (Vin=0) Leaves an RC Circuit we can analyze Penn ESE370 Fall2012 -- DeHon 21 ESE215 problem

22. Zero-th Order Tells us how switches set (Vin=0) Look at middle stage (V2) Penn ESE370 Fall2012 -- DeHon 22 What is equivalent circuit of load at V2?

23. Zero-th Order Tells us how switches set (Vin=0) Look at middle stage (V2) Penn ESE370 Fall2012 -- DeHon 23 What is equivalent output circuit for first pair of transistors driving V2?

24. Zero-th Order Tells us how switches set (Vin=0) Look at middle stage (V2) Penn ESE370 Fall2012 -- DeHon 24 What is relevant circuit?

25. Zero-th Order Tells us how switches set (Vin=0) Look at middle stage (V2) Penn ESE370 Fall2012 -- DeHon 25 What is relevant circuit? Gnd Vdd

26. Zero-th Order Tells us how switches set (Vin=0) Look at middle stage (V2) Penn ESE370 Fall2012 -- DeHon 26 What is delay of this stage? (charging V2 when Vin switch Vdd  0)

27. What more does first-order model tell us? Delay Quasistatic behavior Voltage settling with resistive loads –At least some basis for reasoning Penn ESE370 Fall2012 -- DeHon 27

28. What is this leaving out? Penn ESE370 Fall2012 -- DeHon 28

29. What is this leaving out? Penn ESE370 Fall2012 -- DeHon 29

30. What leaving out? What happens at intermediate voltages –Not rail-to-rail Details of dynamics, including… –Input not transition as step –Intermediate drive strengths change with Vgs Isn’t really 0 current below threshold Penn ESE370 Fall2012 -- DeHon 30

31. Engineering Control Vth – process engineer Drive strength (R on )– circuit engineer control with sizing transistors Supply voltages (Vdd) –range set by process –detail use by circuit design Penn ESE370 Fall2012 -- DeHon 31

32. Engineering Control: Threshold Penn ESE370 Fall2012 -- DeHon 32

33. Engineering Control: Drive Strength Penn ESE370 Fall2012 -- DeHon 33

34. Rs and Cs Penn ESE370 Fall2012 -- DeHon 34

35. Wire Capacitance Penn ESE370 Fall2012 -- DeHon 35

36. Wire Capacitance Penn ESE370 Fall2012 -- DeHon 36

37. Wire Resistance Penn ESE370 Fall2012 -- DeHon 37

38. Wire Resistance Penn ESE370 Fall2012 -- DeHon 38

39. Wire Resistance Sanity check –Wire twice as long = resistors in series –Wire twice as wide = resistors in parallel Penn ESE370 Fall2012 -- DeHon 39

40. There are always Rs and Cs Every wire (connection) has resistance Every wire has capacitance (Every wire has inductance) Modeling vs. discrete components Dominant effects –Rbig + Rsmall ≈ Rbig (Rwire << Ron)? –Cbig || Csmall ≈ Cbig (Cwire<<Cg) ? Penn ESE370 Fall2012 -- DeHon 40

41. Admin Posted –Lab Instructions –Homework 2 Homework 1 due tomorrow –(make sure clear on blackboard turnin) Lab on Friday –Read lab instructions and HW2 –Bring USB drive Monday back in Lecture Penn ESE370 Fall2012 -- DeHon 41

42. Penn ESE370 Fall2012 -- DeHon 42 MOSFET

43. Big Ideas MOSFET Transistor as switch Purpose-driven simplified modeling –Aid reasoning, sanity check, simplify design Analysis methodology –zero-th order to understand switch state (logic) –First-order to get equivalent RC circuit (delay) New perspective on Rs and Cs Penn ESE370 Fall2012 -- DeHon 43