1. Current Balance A 2-phase single output configuration is used here as an example

2. Current Balance The sensed current is amplified with a ratio of 13 and then is subtracted from COMP. The subtracted voltage Ve is then compared with the ramp to generate the duty cycle command. COMP is the same for the two channels. Also, the two ramps are also the same in magnitude although with 180 degree phase shift. So, i.e. 1st channel has current, then Ve1 is decreased, hence the duty cycle of 1st channel is reduced that will reduce the current in the channel and then bring back to current balance.

3. Current Balance Ipk: inductor peak current; Vshr: ramp valley votage; Vramp: it is equal to 0.5V; : this term compensates the duty cycle with different load current; The currents are balanced because they have the same COMP and Vshr. The Rdson and DCR might be slightly different for the two channels, however, the term is too small compared to the other terms. It is almost negligible. Therefore, the above equation becomes: The inductor DCR tolerance will then be the peak current tolerance.

4. Current Balance To parallel modules without optimized phase shift, Single pin is required for current balance. The TRK1 pin in the slave chip should be tied to +5V to disable the error amplifier. The COMP pins are tied together to force current balancing. Vshr pins do not have to be connected because Vshr is very accurate between chips. Its tolerance is a few mVs. So with the same equation shown above, we can find the paralleled channels are current balanced.

5. Current Balance A system EVM board is configured as a 2-phase single output converter. Vin=12V, Vo=1V, fsw=330kHz, Io=20A. Ch1, Ch2: switch node for 1st and 2nd phase Ch3, Ch4: Inductor Current for 1st and 2nd phase