1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Design and architecture 1 Adders: –Carry Lookahead Adder (CLA) Fast Optimization –Reduced foot print by limiting addition to 4-bits per stage –Introduced pipelining to sum up the 24-bits (6x 4-bits) –Carry Save Adder (CSA) Fast Result is not binary –Carry Save adder (using 5:3 compressors) Fast Result is not binary Extra carry signal

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Design and architecture 2 Multiplier: –Fixed coefficient canonical signed digit(CSD) multiplier Invert, shift and add operations Optimizations –Down-scaled coefficient word length to 9-bits signed –Semi-Symmetrical coefficients → One less multiplier –Maximum 3 partial products plus 1 sign correction bit Result is not binary

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 Design and architecture 4 x_in c 5:3 comp CSA Optional sum carry

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Design and architecture 5 36x registers14x 5:3 compressors9x multipliers N = 13 N = 0 pipelined cl-adder x_in 3x each y_out

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Synthesis Pipelined Carry-Lookahead-Adder Carry-Save-Adder 5:3 Compressor 9x Multipliers Synthesis Estimates Frequency f1250 Mhz (0.8ns) Area34355.3 uM Registers1748 P dynamic48.9726 mW P leakage2.5593 uW # Pipeline Stages8 Metric 1.558 * 10^16 Mhz^3/nW

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Simulation Results

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 In All 1.Observations: –Gate-Level synthesis at lower level, using different libraries and components –More optimization capabilities –Compacter and faster implementation