1. Current “thinking” about CMS phase 2 pixel: Global system and power 1 Jorgen Christiansen, CERN/PH-ESE

2. What is new Not much as only few people (~none) currently works on the phase 2 pixel system Not much as only few people (~none) currently works on the phase 2 pixel system People engaged in RD53 for critical pixel chip People engaged in RD53 for critical pixel chip Phase 1 upgrade with critical schedule Phase 1 upgrade with critical schedule Some people looking into phase 2 pixel sensors Some people looking into phase 2 pixel sensors CMS phase 2 upgrade TP in draft version (not yet public) with a rather generic chapter on phase 2 pixel and its electronics CMS phase 2 upgrade TP in draft version (not yet public) with a rather generic chapter on phase 2 pixel and its electronics Very draft document with an outline of phase 2 pixel system and requirements to a phase 2 pixel chip/system: ~35 pages Very draft document with an outline of phase 2 pixel system and requirements to a phase 2 pixel chip/system: ~35 pages Evolving document with current knowledge about: Basic Layout Basic Layout Hit rate estimates Hit rate estimates Global system: modules, chips, links, power Global system: modules, chips, links, power Readout Readout Power distribution guesstimates (two stage DC/DC and serial) Power distribution guesstimates (two stage DC/DC and serial) Pixel chip requirements Pixel chip requirements SEU rate estimates SEU rate estimates Etc. Etc. Not yet circulated within CMS pixel community (within ~2 weeks) 2

3. Rate estimates MC simulations with “phase 2 layout” but still with current pixel size (150x100um 2 ) MC simulations with “phase 2 layout” but still with current pixel size (150x100um 2 ) Hit rates should be the same if scaling pixel size dimension and sensor thickness with same factor (keeping cluster size in pixel units the same): 150um -> 50um, 300um -> 100um Hit rates should be the same if scaling pixel size dimension and sensor thickness with same factor (keeping cluster size in pixel units the same): 150um -> 50um, 300um -> 100um L1: 2GHz/cm 2, 50KHz per 50x50um 2 pixel at PU=140 L1: 2GHz/cm 2, 50KHz per 50x50um 2 pixel at PU=140 3

4. Layout sketches and modularity 4

5. System summary Barrel L1L2L3L4Inner disksOuter disksTotal r (mm)306810216045 - 8585-160 Pixel size (um 2 ) 50x50 100x10050x50100x100 Track rate: (relative) 500MHz/cm 2 1/41/81/161/51/10 Hit rate: PU140: (PU200) 2GHz/cm 2 (3GHz/cm 2 ) 1/41/81/161/51/10 Facets: Per ladder: 12 8 14 8 22 8 32 81426 Module size chips: mm: 1 x 4 20 x 80 2 x 4 40x80 2 x 2 40x40 2 x 4 40x80 Disks 2 x 72 x 10 Modules961121762561965201356 Chips3848961408204878441609680 Hits per chip per Bx 2005025134020 Event size per chip (bits) 486812646643641024544 Event size (KBytes)2281381149198276946 Data rate per chip @ 500KHz trg. Gbits/s 2.430.630.330.180.510.27 Data rate per module Gbits/s 9.735.062.661.462.052.18 E-links per module @1.2Gbs/s 8 (16)4 (8)2 (4) E-links @ 1.2Gbs/s 768 (1536) 448 (896) 352 (704) 512 (1024)392 (784) 1040 (2080) 3512 (7024) 5

6. E-links Low rate (1.2Gbits/s) serial to remote LPGBT Low rate (1.2Gbits/s) serial to remote LPGBT Rate that makes sense for input to LPGBT (10Gbits/s) Rate that makes sense for input to LPGBT (10Gbits/s) Speed could be seriously limited by radiation damage Speed could be seriously limited by radiation damage 2x, 4x as option 2x, 4x as option Max 8 (4) per chip Max 8 (4) per chip Data merging from max 8 pixel chips Data merging from max 8 pixel chips 3500 links, 2m twisted pair (or flex cable) 3500 links, 2m twisted pair (or flex cable) 36AWG shielded twisted pair: 2.5kg copper 36AWG shielded twisted pair: 2.5kg copper Alu - Cu without shield: 0.4kg Alu + 0.2kg copper Alu - Cu without shield: 0.4kg Alu + 0.2kg copper 6 100um sensors+100um pixel chips = ~2kg Si

7. Power pesstimates High rate regions with 50x50um 2 pixels: Barrel L1 Medium rate regions with 50x50um 2 pixels: Barrel L2, L3, Inner disks Low rate regions with 100x100um 2 pixels: Barrel L4, Outer disks Total power (very conservative: 2x ?) : 15.8KW 7 Analog power supply1.2v Pixel analog current (50x50um 2 )6uA per pixel Pixel analog current (100x100um 2 )10uA per pixel Digital power supply0.8v Digital power density, low rate0.2W/cm 2 Digital power density, medium rate0.25W/cm 2 Digital power density, high rate0.5W/cm 2 High rate pixel chip (50x50): Analog (1.2v) current per chip0.96A Digital (0.8v) current per chip2.50A Total chip power (high rate 50x50)3.15W Medium rate pixel chip (50x50): Analog (1.2v) current per chip0.96A Digital (0.8v) current per chip1.25A Total chip power (med rate 50x50)2.15W Low rate pixel chip (100x100): Analog (1.2v) current per chip0.40A Digital (0.8v) current per chip1.00A Total chip power (low rate 100x100)1.28W

8. Two stage DC/DC 8 Copper mass for local DC/DC power cabling DistanceMax voltage drop 0.1v0.2v0.4v 0.5m5.27kg2.63kg1.32kg 1.0m21.08kg10.54kg5.27kg 2.0m84.31kg42.16kg21.08kg Aluminium mass for local DC/DC power cabling DistanceMax voltage drop 0.1v0.2v0.4v 0.5m2.67kg1.33kg0.67kg 1.0m10.66kg5.33kg2.67kg 2.0m42.65kg21.32kg10.66kg On-chip DC/DC: switched capacitor On-chip capacitors ? Analog: factor 2 + LDO Digital: factor 3 Is it feasible to have higher conversion factor on-chip ? FEAST like

9. Two stage DC/DC Critical to get remote DC/DC as close to pixel modules as possible Realistic to make on-chip DC/DC for 1Grad ? Realistic to make on-chip DC/DC for 1Grad ? Higher on-chip conversion factor ? Higher on-chip conversion factor ? Required to cool cables ? Required to cool cables ? Material in forward region within phase 2 coverage Material in forward region within phase 2 coverage 9 Two stage DC/DC overviewunit Analog pixel chip voltage1.2V Digital pixel chip voltage0.8V Intermediate DC/DC voltage2.6V Local power converter efficiency0.9 local analog DC/DC conversion ratio2 Analog LDO voltage drop0.1V Local digital DC/DC conversion ratio3 Total pixel chip power15.80kW Power loss in local converters2.40kW Total power to local converters18.20kW Local power routing distance1.00m Max voltage drop on power wire0.20V Power loss in cables2.80kW Total power delivered by remote DC/DC21.00kW Minimum module current (inner disks)3.84A Minimum power wire diameter (inner disk) 0.83mm Max module current (L2, L3)7.69A Max power wire diameter (L2,L3)1.17mm Number of power cables (with 2 wires)1356 Total power cable mass (Alu)5.33kg

10. Serial A. Between chips on same module Good: No power chaining between modules (failure propagation) Good: No power chaining between modules (failure propagation) Bad: Chips on same module at different potentials: communications, sensor interface Bad: Chips on same module at different potentials: communications, sensor interface B. Between modules Good: All chips on same module at same potential Good: All chips on same module at same potential Bad: Risk of failure propagation across many modules Bad: Risk of failure propagation across many modules Has been evaluated/tested by ATLAS pixel with FEI chips. “Implies” a chain/stave structure with possibility to short circuit failing modules 10

11. ATLAS serial power R&D R&D program since 2003 !. R&D program since 2003 !. Based on very flexible on-chip shunt-LDO (M. Karagounis) Based on very flexible on-chip shunt-LDO (M. Karagounis) Can connect multiple in series and in parallel Can connect multiple in series and in parallel Has two control loops to allow this Has two control loops to allow this Will be mapped to 65nm in RD53 framework Will be mapped to 65nm in RD53 framework Very promising results Very promising results No major difference in noise and effective threshold No major difference in noise and effective threshold Separate protection chip under development Separate protection chip under development Look at: https://indico.cern.ch/event/334980/session/1/contribution/44/material/slides/0.pdf https://indico.cern.ch/event/334980/session/1/contribution/44/material/slides/0.pdf https://indico.cern.ch/event/334980/session/4/contribution/27/material/slides/1.pdf 11

12. Block Diagram IP Block: Shunt-LDO Regulator ParameterValue Sizetbd. Supply voltage (Vin)1.4 - 2.5V (very likely lower) Supply current200 - 550 mA Output voltage1.2V – 1.5V Load Regulation Line Regulation2,5 % PSRR25dB @ 400 kHz ; -20dB @ 1MHz Output Capacitor2.2 µF (low ESR) (go to cap-less) Minimum quiescient current200 µA Temperature range-20C +50C Max variation (PVT, mismatch)5% Max variation (1Grad, 10 16 n/cm 2 )tbd. Metal layers usedFull metal stack Resistortbd. Capacitortbd. Active element usedStandard CMOS Status (01.10.2014)First simulations in 65 nm Designer (Email)michael.karagounis@hshl.de I/O signalsFunction IinSupply current/voltage input IoutSupply current output/ ground VoutRegulated output voltage StatusDate Initial specQ2 2014 SchematicQ4 2014 LayoutQ1 2015 Final specQ2 2014 Prototype 1 submissionQ1 2015 Prototype characterizedQ2 2015 Prototype 2 submissionQ3 2015 Prototype 2 characterizedQ4 2015 Full IP availableQ1 2016 Schedule

13. Serial powering on module Only use on-chip LDO Only use on-chip LDO Simple Simple Higher power loss (but still very attractive) Higher power loss (but still very attractive) Use of on-chip DC/DC Use of on-chip DC/DC Complicated Complicated 13 Aluminium weight for serial powering DistanceMax cable voltage drop 0.1v0.2v0.4v 0.5m0.95kg0.47kg0.24kg 1.0m3.79kg1.89kg0.95kg 2.0m15.16kg7.58kg3.79kg

14. Serial power Serial power overviewunit Analog pixel chip voltage1.2V Digital pixel chip voltage0.8V Total pixel chip power15.80kW Local Shunt voltage1.3V Analog LDO voltage drop0.1V Digital LDO voltage drop0.5V Power loss in local LDO's6.10kW Total power to modules21.90kW Local power routing distance1.00m Max voltage drop on power wire0.20V Power loss in cables1.00kW Total power delivered22.89kW Minimum module current (L4)1.40A Minimum power wire diameter (L4)0.50mm Max module current (L1)3.46A Max power wire diameter (L1)0.79mm Minimum module voltage (L1, ID)5.20V Maximum module voltage (L2,L3,L4, OD)10.40V Number of power cables (with 2 wires)1356 Total power cable mass1.89kg 14

15. Comparison Serial power looks very attractive Serial power looks very attractive “Simple” chip implementation: Shunt – LDO “Simple” chip implementation: Shunt – LDO ~1/3 material in power cables ~1/3 material in power cables ~1/3 power losses in cables (less worries about cabling cooling) ~1/3 power losses in cables (less worries about cabling cooling) Major worries: Noise injection and failure propagation Major worries: Noise injection and failure propagation R&D and extensive testing required R&D and extensive testing required 15 Two stage DC/DC Serial powering Total pixel chip power consumption 15.8kW Local on-chip power conv. losses 2.4kW6.1kW Total module power dissipation 18.2kW21.9kW Power cable losses (1m)2.8kW1.0kW Total power21.0kW22.9kW Power cabling (Alu)5.33kg1.9kg

16. Pixel chip requirements Initial list of requirements Initial list of requirements Analog requirements (from RD53 analog WG) Analog requirements (from RD53 analog WG) Functional requirements Functional requirements Triggered: Rate, Latency, consecutive triggers,, Triggered: Rate, Latency, consecutive triggers,, Buffering requirements and acceptable hit losses Buffering requirements and acceptable hit losses Non triggered (for tests) Non triggered (for tests) IO requirements IO requirements Reliability/availability requirements (SEU) Reliability/availability requirements (SEU) Safety functions Safety functions Test functions: Sensor, chip testing, bump-bonding, system testing, threshold adjust, calibration, etc. Test functions: Sensor, chip testing, bump-bonding, system testing, threshold adjust, calibration, etc. Exotic options: Fast OR, self trigger, sub ns timing, Pixel luminositor monitoring, etc. Exotic options: Fast OR, self trigger, sub ns timing, Pixel luminositor monitoring, etc. 16

17. SEU rate guesstimates Basic assumptions: Basic assumptions: 65nm storage cell (FF, latch, RAM) high energy hadron cross-section: ~10 -14 65nm storage cell (FF, latch, RAM) high energy hadron cross-section: ~10 -14 HEH rate: 500MHz/cm 2 (inner layer and very conservative) HEH rate: 500MHz/cm 2 (inner layer and very conservative) EOC: 1kbit config + 1Kbit state EOC: 1kbit config + 1Kbit state Single Event Functional Interrupt (SEFI): ~100s Single Event Functional Interrupt (SEFI): ~100s Requirement: less than one per day per chip Requirement: less than one per day per chip Full TMR required Pixel cell: 16bit config + 16bit state: ~160k pixels per chip Pixel cell: 16bit config + 16bit state: ~160k pixels per chip 10 pixel cells per chip affected every second 10 pixel cells per chip affected every second Can possibly also affect function of whole chip (e.g. token passing) Can possibly also affect function of whole chip (e.g. token passing) Full TMR required Hit data corruption: 24 bit, 10us storage Hit data corruption: 24 bit, 10us storage Hit data corruption probability: ~10 -9 Hit data corruption probability: ~10 -9 Requirement: < 10 -4 Requirement: < 10 -4 No SEU protection of hit data required in data buffers 17

18. Background/loopers rejection ~1ns time resolution could possibly be used to tag/reject background/slow looper/etc. ~1ns time resolution could possibly be used to tag/reject background/slow looper/etc. This only has a ~20% tagging/rejection potential This only has a ~20% tagging/rejection potential Does not seem worth the effort/power Does not seem worth the effort/power 18

19. Feedback Early draft document that has not yet circulated Early draft document that has not yet circulated I will circulate within a few weeks I will circulate within a few weeks Happy to get any feedback Happy to get any feedback This could possibly become a common ATLAS/CMS document This could possibly become a common ATLAS/CMS document Overview of both ATLAS and CMS pixel systems Overview of both ATLAS and CMS pixel systems Power distribution aspects (material) Power distribution aspects (material) Considerations on readout links (material, rates, etc.) Considerations on readout links (material, rates, etc.) Common requirements to pixel chip (RD53) Common requirements to pixel chip (RD53) Pixel chip architecture and implementation issues Pixel chip architecture and implementation issues 19

20. Whats now needed/urgent Review of specific/critical system aspects: Review of specific/critical system aspects: Power distribution Power distribution Critical for system, pixel chip, material budget (physics),, Critical for system, pixel chip, material budget (physics),, Readout links and interface with LPGBT Readout links and interface with LPGBT LPGBT specification group will soon start LPGBT specification group will soon start Pixel module design Pixel module design Serious Lack of CMS people for phase 2 pixel. We need to put at least one name/group per point !. Interest enough to make dedicated review meetings for powering and readout ? We should do as much as we can in collaboration with ATLAS ( “RD53 extension”). (Otherwise we will just hang on to what ATLAS is doing) 20