1. Lecture 23: 11/26/2002CS170 Fall 20021 CS170 Computer Organization and Architecture I Ayman Abdel-Hamid Department of Computer Science Old Dominion University Lecture 23: 11/26/2002

2. CS170 Fall 20022 Outline Appendix B Combinatorial Logic Clocks Memory Elements

3. Lecture 23: 11/26/2002CS170 Fall 20023 Combinatorial Logic Programmable Logic Array (PLA) Decoders Multiplexors

4. Lecture 23: 11/26/2002CS170 Fall 20024 PLA The sum of products form of logic representation corresponds to a structured-logic implementation called a Programmable Logic Array (PLA) It has a set of inputs and corresponding input complements and two stages of logic.  The first stage is an array of AND gates that form a set of product terms (called minterms)  The second stage is an array of OR gates each of which forms a logical sum of any number of the product terms. Basic form of a PLA

5. Lecture 23: 11/26/2002CS170 Fall 20025 PLA Example 1/2 InputsOutputs ABCDEF 000000 001100 010100 011110 100100 101110 110110 111101 D = ? (Try to derive D as a sum of products) F = A.B.C Number of rows in AND plane equal to number of inputs Number of columns in AND plane equal the number of distinct products Number of columns in the OR plane is equal to the number of columns in the AND place Number rows in the OR plane is equal to the number of outputs

6. Lecture 23: 11/26/2002CS170 Fall 20026 PLA Example 2/2 Show position of AND and OR gates, instead of drawing gates Dots are used on the intersection of a product term signal line and an input line or an output line when AND/OR gate is required This column denotes the product A.B.C And the product is used as input to OR gate to compute D and is F

7. Lecture 23: 11/26/2002CS170 Fall 20027 Decoders 1/2 n-bit input and 2 n outputs where only one output is true for each input combination The output signal corresponds to the binary value of the n-bit input If the value of input is k, then Outk will be true and all other outputs will be false Example: a 3-bit decoder (a 3-to-8 decoder) See truth table on page B-8 Can you design a gate diagram corresponding to the truth table? (assume a 3-input AND gate)

8. Lecture 23: 11/26/2002CS170 Fall 20028 Decoders 2/2 Gate diagram corresponding to truth table on page B-8

9. Lecture 23: 11/26/2002CS170 Fall 20029 Multiplexors 1/2 Select one of n inputs using a control (The output is one of the inputs based on the control value) 2 data inputs require one selector value (n inputs need  log 2 n  selector inputs) When S = 0, C = A When S = 1, C = B C = (A. NOT(S)) + (B. S) (S1,S0) = (0,0)  Output = A0 (S1,S0) = (0,1)  Output = A1 (S1,S0) = (1,0)  Output = A2 (S1,S0) = (1,1)  Output = A3

10. Lecture 23: 11/26/2002CS170 Fall 200210 Multiplexors 2/2 A selection between 32-bit inputs

11. Lecture 23: 11/26/2002CS170 Fall 200211 Clocks Needed in sequential logic to decide when an element that contains state should be updated A clock has a cycle time, with the clock frequency = 1/cycle time All state changes occur on a clock edge (edge-triggered clocking) Either the rising edge or the falling edge is active, and causes state changes to occur

12. Lecture 23: 11/26/2002CS170 Fall 200212 Memory Elements 1/3 All memory elements store state: The output from any memory element depends both on the inputs and on the value that has been stored inside the memory element Unclocked Memory elements (unclocked latch) S-R latch (set-reset latch) built from a pair of NOR gates When neither S nor R are asserted, the cross-coupled NOR gates store the previous values of Q and NOT(Q) If the output Q is 1, the bottom inverter produces a false output (NOT(Q)), which becomes the input to the top inverter, which produces a true output (Q) and so on If S is asserted, the Output Q will be asserted and NOT(Q) will be deasserted If R is asserted then output NOT(Q) will be asserted and Q will be deasserted.

13. Lecture 23: 11/26/2002CS170 Fall 200213 Memory Elements 2/3 Clocked Memory elements (latches and Flip-flops)  The change of state is triggered by the clock  Clocked latch: the state is changed whenever the appropriate inputs change and the clock is true  Flip-flop: state is changed only on a clock edge (Falling edge, Rising edge) A D latch stores the value of its data input signal in its internal memory Two inputs and two outputs  Inputs: data value to be stored (D) and clock signal ©  Outputs: internal state Q and its complement When clock input C is asserted, the latch is open and Q becomes the value of D When C is deasserted, the latch is closed, the value of Q is whatever value was stored the last time the latch was open Assuming Q is false and D changes first

14. Lecture 23: 11/26/2002CS170 Fall 200214 Memory Elements 3/3 A falling-edge D flip-flop The output is stored when the clock edge occurs The D input is sampled on the clock edge, it must be valid for period of time immediately before and immediately after the clock edge Set-up time: the minimum time that the input must be valid before the clock edge Hold time: the minimum time during which the input must be valid after the clock