1. 1 Digital processing applications for DE2 card High Speed Digital Systems Lab Winter 2008/09  Instructor: Mony Orbach  Students : Avner Reisz, Natty Nizri 1 semester project

2. Introduction   The MSS (mixed signal system) from Alex & Rony’s project, combines analog and digital signals.   With the help of Alterra’s DE2, analog signals can be digitally processed after being sampled by the MSS. 2

3. Introduction   This is the case handled: 3

4. 4 Topics  Project goal Project goal Project goal  Signal regulation Signal regulation Signal regulation  Outputs Outputs  Block diagram Block diagram Block diagram  Rates & frequencies Rates & frequencies Rates & frequencies  Time table Time table Time table  The applications The applications The applications  Inputs Inputs

5. 5 Project goal  Writing the DE2-MSS interface in VHDL.  Designing of amplifiers, filters and noise reductions for that interface.  Writing the digital processing applications.

6. Signal regulation  The MSS can get ±1v as input and ±1.4v as output. In order to enlarge these ranges, we put an attenuator at the input and an amplifier at the output.  In addition, the unipolar output of the MSS is turned into a bipolar signal. (the amplifier kills the 2.5v DC) 6

7. 7 Inputs DE2 Function generator MSS 8-bit BUS (100 kHz) Attenuator + LPF 1/10 50 kHz

8. 8 Outputs 8-bit BUS (100 kHz) DE2 MSS Scope Amplifier +LPF 10/1.4 50 kHz

9. 9 Block diagram Function generator Scope DE2 MSS Amp.att.

10. 10 Rates & frequencies: MSS  BW: 20Hz – 50kHz*  Input:  ± 1v (attenuated from ±10v)  Output:  2.5 ± 1.4v (then amplified to ±10v)

11. 11 Rates & frequencies: DE2  I/O:  8 bit bus  100kHz  Cyclone II  50/27 MHz

12. The Aplications: 12 1. Saturation: Cuts to the signal to a max value whenever crossing it. 2. Time stretch: Stretches the signal in time. (This is actually like freq. reduce) 3. DC: Applies a DC value of choice. (e.g. Vrms or peak of the original signal). 4. 4. Division: Divides the signal (letting the user choose the factor is an option..) 5. Filter.

13. 13 Time table Information gathering Information gathering Characterization presentation Characterization presentation Study sampling & reconstruction Study sampling & reconstruction Input decrease solution + LPF Input decrease solution + LPF Output normalization + LPF Output normalization + LPF Quartus acquaintance Quartus acquaintance VHDL review VHDL review Simple test application (+ test) Simple test application (+ test) Midterm presentation Midterm presentation Algorithm design Algorithm design VHDL design (+ test) VHDL design (+ test) Week1234567891011121314151617