1. LHCb – Calo Upgrade Meeting – 20th October 2013 – CERN Upgrade Calo FE Review Comments: Analog D. Gascon for the LHCb calo group Universitat de Barcelona Institut de Ciències del Cosmos ICC-UB

2. I. Introduction This is just personal opinion to start discussion A deeper discussion probably needs a F2F meeting as proposed by Frédéric 2

3. I. General remarks from the reviewers Demands on spill-over, dead-time, efficiency are solved in the analog domainDemands on spill-over, dead-time, efficiency are solved in the analog domain  Recommendation is to investigate whether digital filtering could be considered after ADC conversion to relax the requirements on the analog circuitry  Major change of the philosophy  Test bench/beam measurements indicate that the performances are in the specifications Does it means to perform waveform digitization in real time?  What is the required sampling rate? Probably > 200 MS/s  Digital becomes very complex Can ProASIC FPGA do it ?  It may work but is complete change of phylosophy I’d only considere it if we face a real-stopper in our present design 3

4. I. General remarks from the reviewers Radiation levels in the region of the calorimeter are modest (~ 100 rad/fb-1)Radiation levels in the region of the calorimeter are modest (~ 100 rad/fb-1)  Care must be taken in the selection of the components Many components which had been tested for the present electronics are planned to be re-used for the upgradeMany components which had been tested for the present electronics are planned to be re-used for the upgrade The reviewers endorse the plan to irradiate a complete FE prototypeThe reviewers endorse the plan to irradiate a complete FE prototype Yes, we should plan a radiation test for 2014 Both analogue solutions have to test basic components:  ASIC  OpAmps I agree that it is need to irradiate a complete board But I would recomend to irradiate dedicated boards for those components at the same time 4

5. II. Specific emarks about analog 2 solutions pursued in parallel2 solutions pursued in parallel  ASIC and COTS (Components off the shelf) systems. Both solutions have pros ans cons.  The decision on the adopted solution should be more clearly defined and rely on performances and on the requested intervention on the detector Decission criteria proposal:  The solutions must fulfill requirements Very close, but not the case yet for any (plateau: ASIC & spill-over: COTs)  The test must be done in a significant number of channels (10 to 50) Concern about repeatability of COTS solution as it is –In my opinion we should add 1 OpAmp (impedance isolation)  Consider non-vital aspects: cost, detector intervention, power, requirement of additional complexity (e.g. delay chips)  Personal opinion: The real choice deadline is given by the design of the first FEB We can not make the choice until we have: –A 4 ch ASIC working –> 10 channels based on COTS working (all same resistors: no ch by ch tuning) If the ASIC is chosen at the end I would NOT forget about COTS 5

6. II. Specific emarks about analog The ASIC solution is based on two interleaved integratorsThe ASIC solution is based on two interleaved integrators  The calibration of the two paths should be more clearly addressed  Should the integrator performing the charge measurement be tagged in the data ? Not really clear if calibration is need  Pedestal is not a problem: offset is “killed” by dynamic pedestal subtraction (and the AC coupling)  Gain mismatch between integrators seems to be < 5 % Is it ok ? Nevertheless the DLL generates the 20 MHz clock based on a divider which is synchronously reset with the bunch ID reset  So inherently odd BCID belong to a given integrators and even samples to the other one  So tagging exists by construction and offline correction can be applied if needed 6

7. II. Specific remarks about analog The present prototype implements 2 optionsThe present prototype implements 2 options  Common and separated grounds  The reviewers suggest to have a strongly equipotential ground widely interconnected between ground planes and to adopt it as a baseline It was interesting to test common and separate grounds BUT.. I think that we must follow the philosophy which is followed now in LHCb because we reuse many components (and the detector):  So ground mesh as recommended by reviewers  I think mixing grounding strategies would be very dangerous 7

8. II. Specific remarks about analog In the present analog design spill-over seems to be solved. Nevertheless, it could be considered to remove the effect at the digital levelIn the present analog design spill-over seems to be solved. Nevertheless, it could be considered to remove the effect at the digital level I agree that it would be worth to investigate if it is possible to remove the spill-over by the digital processing  It seems to be of the order of 5 % on average (worst case)  Probably Monte Carlo simulation is needed to evaluate possible drawbacks? Statistical fluctuations ? Possible misidentification of pedestal for next samples ? 8

9. II. Specific remarks about analog The analog front-end (including ADC) requires a large number of phase-adjustable 40 MHz clocks. It is recommended to minimise the number of clocks, and clock resources in the GBTX should be used efficiently. A strategy for correctly aligning the clock phases should be worked out.The analog front-end (including ADC) requires a large number of phase-adjustable 40 MHz clocks. It is recommended to minimise the number of clocks, and clock resources in the GBTX should be used efficiently. A strategy for correctly aligning the clock phases should be worked out. Completely agree to minimize clocks It is enough for a FEB based on COTS solution with GBTX? Additional clock phases are needed for the ASIC  But they are generated in the ASIC  Recent delay chip to test the block seems to be successful The alignment between different clocks phases will be fixed for ever once we test the final prototype  Only need to adjust a common offset to all clocks to phase beam 9

10. II. Specific remarks about analog Slow control of the analog well integrated to the global architecture of the boardSlow control of the analog well integrated to the global architecture of the board  A solution could be found to generate a refresh pulse for the triple voting registers of the SPI interface reset. An ad hoc pulse could be transmitted regularly in the ECS field of the TFC+ECS word to the FE in order to refresh the TMR registers without the need to use a fast command for this purpose Seems to be a good solution  Important to do it in empty bunches or non-data taking periods SPI must be quiet during data taking 10

11. II. Specific remarks about analog The effects of digital clocked activity on the analog circuitry should be investigated as soon as the full prototype of the front-end is available. Resources used for clock generation on the ASIC should be minimised. For example, a single core DLL could be used for the multiple delay lines.The effects of digital clocked activity on the analog circuitry should be investigated as soon as the full prototype of the front-end is available. Resources used for clock generation on the ASIC should be minimised. For example, a single core DLL could be used for the multiple delay lines. Certainly it must be carefully studied  It is a key measurement for a switched solution Ok to minimize DLL cores  But regarding switching noise main problem are inverter chains 11