1. 1 Chapter Seven

2. 2 SRAM: –value is stored on a pair of inverting gates –very fast but takes up more space than DRAM (4 to 6 transistors) DRAM: –value is stored as a charge on capacitor (must be refreshed) –very small but slower than SRAM (factor of 5 to 10) Memories: Review

3. 3 Users want large and fast memories! SRAM access times are 2 - 25ns at cost of $100 to $250 per Mbyte. DRAM access times are 60-120ns at cost of $5 to $10 per Mbyte. Disk access times are 10 to 20 million ns at cost of $.10 to $.20 per Mbyte. Try and give it to them anyway –build a memory hierarchy Exploiting Memory Hierarchy 1997

4. 4 Locality A principle that makes having a memory hierarchy a good idea If an item is referenced, temporal locality: it will tend to be referenced again soon spatial locality: nearby items will tend to be referenced soon. Why does code have locality? Our initial focus: two levels (upper, lower) –block: minimum unit of data –hit: data requested is in the upper level –miss: data requested is not in the upper level

5. 5 Two issues: –How do we know if a data item is in the cache? –If it is, how do we find it? Our first example: – block size is one word of data – "direct mapped" For each item of data at the lower level, there is exactly one location in the cache where it might be. e.g., lots of items at the lower level share locations in the upper level Cache

6. 6 Mapping: address is modulo the number of blocks in the cache Direct Mapped Cache

7. 7 For MIPS: What kind of locality are we taking advantage of? Direct Mapped Cache

8. 8 Taking advantage of spatial locality: Direct Mapped Cache

9. 9 Read hits –this is what we want! Read misses –stall the CPU, fetch block from memory, deliver to cache, restart Write hits: –can replace data in cache and memory (write-through) –write the data only into the cache (write-back the cache later) Write misses: –read the entire block into the cache, then write the word Hits vs. Misses

10. 10 Read: 1. Send the address to the appropriate cache from PC  instruction cache from ALU  data cache 2. Hit: the required word is available on the data lines Miss: send send full address to the main memory, when the memory returns with the data, we write it into the cache Write: 1. Index the cache using bits 15~2 of the address. 2. write both the tag portion and the data portion with word 3. also write the word to main memory using the entire address * Write buffer Hits vs. Misses (Write through)

11. 11 Make reading multiple words easier by using banks of memory It can get a lot more complicated... Hardware Issues

12. 12 Example: 1 clock cycle to send the address 15 clock cycles for each DRAM access initiated 1 clock cycle to send a word of data Cache block of 4 words  miss penalty: one-word-wide bank of DRAMS  1 + 4 X 15 + 4 X1 = 65 clock cycles #bytes transfer / clock cycle = (4 X 4) / 65 = 0.25 2-word-wide bank of DRAMS  1 + 2 X 15 + 2 X1 = 33 clock cycles #bytes transfer / clock cycle = (4 X 4) / 33 = 0.48 4-word-wide bank of DRAMS  1 + 15 + 1 = 17 clock cycles #bytes transfer / clock cycle = (4 X 4) / 17 = 0.94  wider bus: additional buffers at the memory  Interleaving: miss penalty = send addr. To the cache + all 4 banks to access memory simultaneously + send 4 words back to the cache  1 + 1 X 15 + 4 X 1 = 20 clock cycles #bytes transfer / clock cycle = (4 X 4) / 20 = 0.8 Designing the memory system to support caches

13. 13 Increasing the block size tends to decrease miss rate: Use split caches because there is more spatial locality in code: Performance

14. 14 Performance Simplified model: execution time = (execution cycles + stall cycles) X cycle time stall cycles = # of instructions X miss ratio X miss penalty Two ways of improving performance: –decreasing the miss ratio –decreasing the miss penalty What happens if we increase block size?

15. 15 Increasing the block size –decreasing miss rate  spatial locality –increasing miss rate  decreasing # blocks that can be held in the cache Block transfer –Early restart: to resume execution as soon as the request word of the block is returned –Requested word first (critical word first): the requested word is transferred from the memory to the cache first. The remainder of the block is then transferred, starting with the address after requested word and wrapping around the beginning of the block. Taking advantage of spatial locality

16. 16 Example: For gcc: instruction miss rate : 2% data miss rate: 4% without any memory stall CPI = 2  perfect cache miss penalty: 40 cycles for all misses  Instruction miss cycle = 2% X 40 X IC = 0.8 IC data miss cycle = 4% X 40 X IC X 0.36 = 0.56 IC  total # memory stall cycles = 1.36 IC  CPI with memory stall = 2 + 1.36 = 3.36  the performance with the perfect cache is better by 3.36 / 2 = 1.68  Using faster clock rate (double) miss penalty = 40 X 2 = 80 cycles total miss cycles per instruction = 2% X 80 + 36% X 4% X 80 = 2.75 cycles performance with fast clock / performance with slower clock = 3.36 / ( (2 + 2.75) X 0.5) = 1.41  increasing the clock rate  increasing the memory stall cycles  higher performance Calculating cache performance

17. 17 Compared to direct mapped, give a series of references that: –results in a lower miss ratio using a 2-way set associative cache –results in a higher miss ratio using a 2-way set associative cache assuming we use the “least recently used” replacement strategy Decreasing miss ratio with associativity

18. 18 An implementation

19. 19 Performance

20. 20 Decreasing miss penalty with multilevel caches Add a second level cache: –often primary cache is on the same chip as the processor –use SRAMs to add another cache above primary memory (DRAM) –miss penalty goes down if data is in 2nd level cache Example: –CPI of 1.0 on a 500Mhz machine with a 5% miss rate, 200ns DRAM access –Adding 2nd level cache with 20ns access time decreases miss rate to 2%  One-level cache: miss penalty to main memory = 200 ns / (2 ns /cycle) = 100 clock cycles -- effective CPI with one-level caching: total CPI = base CPI + memory stall cycles per instruction = 1.0 + 5% X 100 = 6.0  two-level cache: miss penalty for an access to the second-level cache = 20 / 2 = 10 clock cycles total CPI = 1 + primary stalls per instruction + secondary stalls per instruction = 1.0 + 5% X 10 + 2% X 100 = 3.5  The machine with the secondary cache is faster by 6.0 / 3.5 = 1.7 Using multilevel caches: –try and optimize the hit time on the 1st level cache –try and optimize the miss rate on the 2nd level cache

21. 21 Virtual Memory Main memory can act as a cache for the secondary storage (disk) Advantages: –illusion of having more physical memory –program relocation –protection

22. 22 Pages: virtual memory blocks Page faults: the data is not in memory, retrieve it from disk –huge miss penalty, thus pages should be fairly large (e.g., 4KB) –reducing page faults is important (LRU is worth the price) –can handle the faults in software instead of hardware –using write-through is too expensive so we use writeback

23. 23 Page Tables

24. 24 Page Tables

25. 25 Making Address Translation Fast A cache for address translations: translation lookaside buffer

26. 26 TLBs and caches

27. 27 Modern Systems Very complicated memory systems:

28. 28 Processor speeds continue to increase very fast — much faster than either DRAM or disk access times Design challenge: dealing with this growing disparity Trends: –synchronous SRAMs (provide a burst of data) –redesign DRAM chips to provide higher bandwidth or processing –restructure code to increase locality –use prefetching (make cache visible to ISA) Some Issues