1. EKT 221 : Digital 2 Computer Design Basics Date : Lecture : 2 hrs

2. Chapter Overview Part 1 – Datapaths  Introduction  Datapath Example  Arithmetic Logic Unit (ALU)  Shifter  Datapath Representation  Control Word Part 2 – A Simple Computer  Instruction Set Architecture (ISA)  Single-Cycle Hardwired Control Instruction Decoder Sample Instructions Single Cycle Computer Issues  Multiple Cycle Hardwired Control Sequential Control Design Digital 2 will focus on Part 1 Part 2 will be covered in Computer Architecture & Microprocessor. however prior reading is encourage.

3. Part 1 : Datapath Computer Specification  Instruction Set Architecture (ISA) The specification of a computer's appearance to a programmer at its lowest level. It describe all the available instruction set in the computer, where it is kept (address) and how to use it (read).  Computer Architecture A high-level description of the hardware implementing the computer derived from the ISA

4. Part 1 : Datapath The architecture usually includes additional specifications such as speed, cost, and reliability. Simple computer architecture comprise of:  Datapath for performing operations  Control unit for controlling datapath operations A datapath is specified by: a.A set of registers b.The microoperations performed on the data stored in the registers c.A control interface

5. Datapaths : Guiding principles for basic datapaths (Typical): The set of registers  Collection of individual registers  A set of registers with common access resources called a register file  A combination (individual & set of reg.) of the above Microoperation implementation  One or more shared resources for implementing microoperations  Buses - shared transfer paths  Arithmetic-Logic Unit (ALU) - shared resource for implementing arithmetic and logic microoperations  Shifter - shared resource for implementing shift microoperations

6. Block Diagram of a Generic Datapath Four parallel-load registers Two mux-based register selectors Register destination decoder Mux B for external constant input Buses A and B with external address and data outputs ALU and Shifter with Mux F for output select (Function Unit) Mux D for external data input Logic for generating status bits V, C, N, Z

7. Block Diagram of a Generic Datapath Example: R1  R2 + R3 A SelectPlace contents of R2 into Bus A 10 B SelectPlace contents of R3 into the input of MUX B 11 MB SelectPlace the 0 input of MUX B into Bus B 0 G SelectProvide the arithmetic operation A + B ???? (4bits) MF SelectPlace the ALU o/p on MUX F o/p 0 MD SelectPlace the MUX F o/p onto Bus D 0 Destination Select To select R1 as the destination of the data on Bus D 01 Load enable To enable a registerR1 = HIGH Note : G Select must refer to Function Table of Arithmetic Circuit (refer next 3 slides)

8. Arithmetic Logic Unit (ALU) ALU Comprise of:  An arithmetic circuit (add, subtract)  A logic circuit (bitwise operation)  A selector to pick between the two circuits 1 2 3

9. Arithmetic Logic Unit (ALU) ALU Comprise of:  An arithmetic circuit An n-bit parallel adder A block of input logic with 2 selectors S 1 and S 0 G Select (4-bits) * Mode Select (S 2 ) distinguishes between arithmetic and logic operations which actually construct item 1 3

10. Arithmetic Circuit Design Note : X = A Analyse the Circuit: Use G = A + Y + Cin Eg. We can verify for n = 4 bit: A = 1010 B = 0101 For S 1 and S 0 = 00, then G = A + 0 + 0 G = A 1

11. Building the B input Logic Input = S 1, S 0 and B Output = Y Obtain the K-Map Get the Boolean Expression Y = BS 0 + BS 1

12. Building the B input Logic Y = BS 0 + BS 1 Y Example of a 4-bit Arithmetic Circuit

13. Building the Logic Circuit The Logic Circuit performs bitwise operation Commonly : AND, OR, XOR and NOT One Stage of Logic Circuit Note : if 4 bit is wanted, then we have to arrange it in array 2

14. Building the Selector for choosing Arithmetic or Logic Unit 3 One Stage of ALU S 2 = 0 for Arithmetic S 2 = 1 for Logic

15. G SelectProvide the arithmetic operation A + B ???? (4bits) G Select (4-bits) Example: R1  R2 + R3 Therefore; S2 = 0 for Arithmetic operation S1 = 0 S0 = 1 Cin = 0 0010 Answer : 0010 MSB LSB

16. The Shifter  The Shifter Shifts the value on Bus B, placing the result on an input of MUX F  The Shifter can: oShift Right oShift Left  It is obvious that the shifter would be a bidirectional shift register with parallel load

17. 4 Bit Basic Shifter SOperation 00Parallel Load B (B to be passed thru the shifter unchanged) 01Shift Right 10Shift Left

18. Barrel Shifter Sometimes the data need to be shifted ore rotated more than one bit position or in a single clock cycle A Barrel Shifter can perform this by using MUX 2 n input requires 2 n MUX

19. 4-Bit Barrel Shifter A rotate is a shift in which the bits shifted out are inserted into the positions vacated The circuit rotates its contents left from 0 to 3 positions depending on Selector S. Note that a left rotation by three (3) position the same as a right rotation by one position in this 4 bit barrel shifter

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