1. © 2003-2008 BYU 12 REGISTERS Page 1 ECEn 224 Registers

2. © 2003-2008 BYU 12 REGISTERS Page 2 ECEn 224 A 4-Bit Register CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 D Q CLK DQ 44 D Q Could be called a parallel-in/parallel-out register. Why?

3. © 2003-2008 BYU 12 REGISTERS Page 3 ECEn 224 A Shift Register CLK SerIn D Q CLK Q3Q2Q1Q0 Called a serial-in, parallel-out shift register (SIPO)

4. © 2003-2008 BYU 12 REGISTERS Page 4 ECEn 224 SIPO Register (Serial-In/Parallel-Out) CLK SerIn D Q CLK Q3Q2Q1Q0 Parallel-Out

5. © 2003-2008 BYU 12 REGISTERS Page 5 ECEn 224 SISO Register (Serial-In/Serial-Out) CLK SerIn D Q CLK SerOut Useful for delaying a serial bit-stream some number of cycles…

6. © 2003-2008 BYU 12 REGISTERS Page 6 ECEn 224 How to Make Any of These Loadable? D Q CLK DQ 44 This register loads on every clock cycle. How to make it load when told to? D Q CLK DQ 44 An obvious solution… This is incorrect – why? LOAD

7. © 2003-2008 BYU 12 REGISTERS Page 7 ECEn 224 Gated Clocking Is A Bad Thing To Do… D Q CLK DQ LOAD CLK LOAD t AND GatedClock The flip flop gets its clock signal late Thus, its output appears late…

8. © 2003-2008 BYU 12 REGISTERS Page 8 ECEn 224 Gated Clocking Causes different flip flops to load at different times –A form of clock skew –Makes doing timing analysis more difficult –Can lead to circuits which run more slowly –Can lead to circuits which fail at any clock rate

9. © 2003-2008 BYU 12 REGISTERS Page 9 ECEn 224 CLK GatedClock LOAD t CLK-Q D Q CLK Q LOAD D Q FFAFFB CLK QAQA QAQA t AND Value that should be loaded into FFB (‘1’) Value that gets loaded into FFB (‘0’) GatedClock

10. © 2003-2008 BYU 12 REGISTERS Page 10 ECEn 224 CLK GatedClock LOAD t CLK-Q D Q CLK Q LOAD D Q FFAFFB CLK QAQA QAQA t AND Value that should be loaded into FFB (‘1’) Value that gets loaded into FFB (‘0’) GatedClock If t CLK-Q < t AND : FFB loads wrong value

11. © 2003-2008 BYU 12 REGISTERS Page 11 ECEn 224 Globally Synchronous Design One global clock All registers load on that clock’s edge Control over loading done via input forming logic (IFL) Simplifies timing analysis and requirements Makes it possible for even novices to design large, functioning circuits Multi-clock circuits  next semester’s topic

12. © 2003-2008 BYU 12 REGISTERS Page 12 ECEn 224 The Correct Way To Make A Loadable Register (1-Bit) D Q 0101 CLK DIN LOAD Q When LOAD=0, FF loads old value When LOAD=1, FF loads DIN

13. © 2003-2008 BYU 12 REGISTERS Page 13 ECEn 224 A Correct Scenario D Q FFA CLK QAQA D Q 0101 CLK LOAD Q FFB No clock skew Both FF’s load on exactly same clock edge Both Q’s appear at same time Timing analysis greatly simplified

14. © 2003-2008 BYU 12 REGISTERS Page 14 ECEn 224 A Loadable Parallel-In, Parallel-Out Register D Q 0101 CLK DIN(3:0) LOAD Q(3:0) 444 PIPO ? 4

15. © 2003-2008 BYU 12 REGISTERS Page 15 ECEn 224 A Loadable Parallel-In, Serial-Out Register (PISO) CLK D Q 0101 LOAD/SHIFT# D2 CLK D Q 0101 LOAD/SHIFT# D1 CLK D Q 0101 LOAD/SHIFT# D0 SerOut SerIn When LOAD/SHIFT# = 1, register loads D2…D0 When LOAD/SHIFT# = 0, register shifts right This register is always either loading or shifting

16. © 2003-2008 BYU 12 REGISTERS Page 16 ECEn 224 MUX for Register Control Loadable register concept can be generalized to provide any combination of inputs to register –Load, clear, set, enable, left shift, right shift, increment, etc.

17. © 2003-2008 BYU 12 REGISTERS Page 17 ECEn 224 A SISO With An Enable Input CLK D Q 0101 ENABLE SerIn D Q 0101 0101 CLK ENABLE CLK ENABLE SerOut Combination of loadable register with shift register… When ENABLE=0, register doesn’t shift (re-loads old value) When ENABLE=1, register shifts

18. © 2003-2008 BYU 12 REGISTERS Page 18 ECEn 224 A Bidirectional Shift Register D Q Q1 0101 CLK UP/DOWN# D Q Q2 0101 CLK UP/DOWN# TopIn D Q Q0 0101 CLK UP/DOWN# Q1 Q0 BottomIn Q2 Q1

19. © 2003-2008 BYU 12 REGISTERS Page 19 ECEn 224 Uses of Shift Registers Collecting serial input data into a parallel word Shifting out bits of a word Delaying a serial stream by some # of cycles

20. © 2003-2008 BYU 12 REGISTERS Page 20 ECEn 224 A Clearable Counter D Q Q CLK CLR INC Q Q+1 0 Q 444444 2 From there to here, from here to there, interesting circuits are everywhere… (when you have a MUX and some flip flops)

21. © 2003-2008 BYU 12 REGISTERS Page 21 ECEn 224 An Up/Down Counter D Q Q CLK UP/DN# Q-1 44 0101 Q+1 How about an up/down counter + bi-directional shift register design?

22. © 2003-2008 BYU 12 REGISTERS Page 22 ECEn 224 Up/Down Counter + Bi-Directional Shift Register D Q Q CLK Control Q+1 Q-1 Q<<1 Q>>1 444444 2

23. © 2003-2008 BYU 12 REGISTERS Page 23 ECEn 224 An Accumulator D Q Q CLK LOAD 44 0101 + A D Q Q CLK CLR 44 0101 + A 0 This one loads A when LOAD=1 This one loads 0 when CLR=1 Both work, they just have different timings… Values to be added are placed on A input, one per cycle. Register accumulates their sum. 44 Version AVersion B

24. © 2003-2008 BYU 12 REGISTERS Page 24 ECEn 224 Register Files Small memories holding multiple words of data

25. © 2003-2008 BYU 12 REGISTERS Page 25 ECEn 224 Typical Register File DataIn clk Addr regWE RegFile DataOut n n m

26. © 2003-2008 BYU 12 REGISTERS Page 26 ECEn 224 Typical Register File DataIn clk Addr regWE RegFile DataOut Data to be written to register file n n m

27. © 2003-2008 BYU 12 REGISTERS Page 27 ECEn 224 Typical Register File DataIn clk Addr regWE RegFile DataOut Data to be written to register file Data that is read from register file n n m

28. © 2003-2008 BYU 12 REGISTERS Page 28 ECEn 224 Typical Register File DataIn clk Addr regWE RegFile DataOut Data to be written to register file Data that is read from register file Address that reads and writes are for n n m

29. © 2003-2008 BYU 12 REGISTERS Page 29 ECEn 224 Typical Register File DataIn clk Addr regWE RegFile DataOut Data to be written to register file Data that is read from register file Address that reads and writes are for n n m This register will hold 2 m words, each n bits wide

30. © 2003-2008 BYU 12 REGISTERS Page 30 ECEn 224 Typical Register File DataIn clk Addr regWE RegFile DataOut Data to be written to register file Data that is read from register file Address that reads and writes are for Controls whether reading or writing n n m This register will hold 2 m words, each n bits wide

31. © 2003-2008 BYU 12 REGISTERS Page 31 ECEn 224 Typical Register File DataIn clk Addr regWE RegFile DataOut Data to be written to register file Data that is read from register file Address that reads and writes are for Reads are asynchronous (combinational) Writes occur on the clock edge. n n m This register will hold 2 m words, each n bits wide Controls whether reading or writing

32. © 2003-2008 BYU 12 REGISTERS Page 32 ECEn 224 Building a Register File Reg0 Reg1 Reg2 Reg3 Reg4 Reg5 Reg6 Reg7 Write Decoder Addr regWE Register write signals DataInclk 8:1 MUX DataOut m=3 n nnnnnnnnn

33. © 2003-2008 BYU 12 REGISTERS Page 33 ECEn 224 Building a Register File Reg0 Reg1 Reg2 Reg3 Reg4 Reg5 Reg6 Reg7 Write Decoder Addr regWE Register write signals DataInclk 8:1 MUX DataOut Asynchronous read: just a MUX m=3 n nnnnnnnnn

34. © 2003-2008 BYU 12 REGISTERS Page 34 ECEn 224 Building a Register File Reg0 Reg1 Reg2 Reg3 Reg4 Reg5 Reg6 Reg7 Write Decoder Addr regWE Register write signals DataInclk 8:1 MUX DataOut Asynchronous read: just a MUX m=3 n nnnnnnnnn Loadable registers

35. © 2003-2008 BYU 12 REGISTERS Page 35 ECEn 224 Building a Register File Reg0 Reg1 Reg2 Reg3 Reg4 Reg5 Reg6 Reg7 Write Decoder Addr regWE Register write signals DataInclk 8:1 MUX DataOut Asynchronous read: just a MUX m=3 n nnnnnnnnn Loadable registers 3:8 Decoder with enable

36. © 2003-2008 BYU 12 REGISTERS Page 36 ECEn 224 Loadable Register Reg0 Reg1 Reg2 Reg3 Reg4 Reg5 Reg6 Reg7 Register write signals DataInclk n n n n n n n n n Reg k clk n Load D Q DataIn regWE k QkQk n

37. © 2003-2008 BYU 12 REGISTERS Page 37 ECEn 224 Write Decoder Write Decoder Addr regWE Register write signals m=3 3:8 Decoder Addr m=3 regWE Register write signals

38. © 2003-2008 BYU 12 REGISTERS Page 38 ECEn 224 Multi-Ported Register File Reg0 Reg1 Reg2 Reg3 Reg4 Reg5 Reg6 Reg7 Write Decoder WAddrWE Register write signals DataInclk RAddr 8:1 MUX DataOut One write port, one read port. Different write and read addresses Can be reading from one location on same cycle you write to another location

39. © 2003-2008 BYU 12 REGISTERS Page 39 ECEn 224 Multi-Ported Register File Reg0 Reg1 Reg2 Reg3 Reg4 Reg5 Reg6 Reg7 Write Decoder WAddrWE Register write signals DataInclk RAddr1 8:1 MUX Raddr2 DataOut1 DataOut2 One write port Two read ports Can be reading from two locations on same cycle you write to another location Useful for microprocessor design

40. © 2003-2008 BYU 12 REGISTERS Page 40 ECEn 224 Memories vs. Register Files Random Access Memory (RAM) is similar to a register file –Stores many multi-bit words for reading/writing RAM usually only single-ported RAM usually much, much larger –Mbytes instead of bytes RAM implementation conceptually the same as register file –Transistor-level implementation different due to size/usage characteristics RAM design beyond the scope of this class