1. Low-Voltage Inhibit Module MTT48 12 - 1 M LOW VOLTAGE INHIBIT MODULE (LVI)

3. Low-Voltage Inhibit Module MTT48 12 - 3 M Module Objective By the end of this module you should be able to: Understand LVI system Understand LVI control Module exercise: Initialize the LVI module for Forced Reset when power drops below the trip point.

4. Low-Voltage Inhibit Module MTT48 12 - 4 M LOW VOLTAGE INHIBIT (LVI) MODULE 68HC08 CPU System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) Direct Memory Access Module (DMA) Serial Communications Interface (SCI) Internal Bus (IBUS) Serial Peripheral Interface (SPI) Random Access Memory (RAM) Electronically Programmable ROM LVI COP Monitor ROM IRQ BREAK RESET Monitors the V DD voltage Programmable LVI reset Programmable power consumption Write-protected status and control register

5. Low-Voltage Inhibit Module MTT48 12 - 5 M LVI Block Diagram LOW V DD LVIRST V DD > LVI TRIP = 0 V DD < LVI TRIP = 1 LVIOUT LVIPWR DETECTOR V DD LVI RESET (FROM MOR) LVISTOP (FROM MOR) STOP INSTRUCTION

6. Low-Voltage Inhibit Module MTT48 12 - 6 M RESET: UNAFFECTED BY RESET WRITE: MOR READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD LVI Enable in Stop Mode (LVISTOP) –If LVIPWR bit is at logic one, LVISTOP enables the LVI modules to operate during stop mode –1 = LVI not disabled by STOP instruction –0 = LVI disabled by STOP instruction LVI Reset (LVIRST) –Enables reset when LVIOUT is set –MPU remains in reset until V DD rises above LVI TRIP –Allow LVI SETTLE time before enabling 1 = LVI reset enabled 0 = LVI reset disabled LVI Power Enable (LVIPWR) –Applies power to the LVI analog circuitry –Disabling will stop current drain form the LVI –1 = Power applied –0 = Power not applied LVI CONTROL

7. Low-Voltage Inhibit Module MTT48 12 - 7 M LVI Status Flag RESET:00000000 WRITE: READ:LVIOUT LVISR 0 00 0 000 LVI Status Register (LVISR) Used to monitor the state of V DD Flags V DD voltages below LVI TRIPF –LVIOUT Bit Indication VDDLVIOUT V DD > LVI TRIPF 0 V DD < LVI TRIPF 1 LVI TRIPF < V DD < LVI TRIPR Previous Value Allow LVI SETTLE time before polling

8. Low-Voltage Inhibit Module MTT48 12 - 8 M Additional Information - Low Power Modes - Low Power modes STOP –When LVIPWR = 1, the LVI is active after a Stop WAIT –When LVIPWR = 1, the LVI is active after a Wait –A LVI Reset will bring the MCU out of Wait mode

9. Low-Voltage Inhibit Module MTT48 12 - 9 M Register Summary RESET: UNAFFECTED BY RESET WRITE: MOR READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD RESET:00000000 WRITE: READ:LVIOUT LVISR 0 00 0 000