1. Chapter 0 ComBinaTionaL loGic deSign ComBinaTionaL loGic deSign EKT 221 / 4 DIGITAL ELECTRONICS II

2. deSiGn conCepTs –Design Procedure –CAD Tools –Propagation Delay –Programmable Logic

3. Block Diagram of Combinational Circuit

4. Design Topics Modern digital design –Techniques & tools for complex circuits & systems design Some important concepts –CAD tools, HDL, logic synthesis, design hierarchy, top-down design

5. Design Hierarchy Approach to design complex digital system –e.g. VLSI circuits “Divide & Conquer” approach –Break up circuit into smaller pieces / blocks –Interconnect the blocks to form complete circuit

6. Hierarchical Design To control the complexity of the function mapping inputs to outputs: ◦ Decompose the function into smaller pieces called blocks ◦ Decompose each block’s function into smaller blocks, repeating as necessary until all blocks are small enough ◦ Any block not decomposed is called a primitive block ◦ The collection of all blocks including the decomposed ones is a hierarchy

7. Hierarchical Design Example: 9-input parity tree (see next slide) ◦ Top Level: 9 inputs, one output ◦ 2nd Level: Four 3-bit odd parity trees in two levels ◦ 3rd Level: Two 2-bit exclusive-OR functions ◦ Primitives: Four 2-input NAND gates ◦ Design requires 4 X 2 X 4 = 32 2-input NAND gates

8. Example : 9 – input odd function

9. Design Hierarchy Concepts 1. Reduces complexity of schematic diagram 2. Reuse of blocks –One block is used multiple times –Cascaded –“Functional blocks”

10. Diagrams Representing Hierarchy

11. Top – Down Design Describe circuit function by text, including constraints on cost, performance & reliability Divide circuit into hierarchy levels

12. Bottom – Up Design Used to design certain portions of big design Starts with design of functional blocks –So that functional blocks can be reused multiple times

13. Top-Down versus Bottom-Up A top-down design proceeds from an abstract, high-level specification to a more and more detailed design by decomposition and successive refinement A bottom-up design starts with detailed primitive blocks and combines them into larger and more complex functional blocks

14. Top-Down versus Bottom-Up Designs usually proceed from both directions simultaneously ◦ Top-down design answers: What are we building? ◦ Bottom-up design answers: How do we build it? Top-down controls complexity while bottom-up focuses on the details.

15. Computer Aided Design (CAD) Schematic capture tools –D–D–D–Drawing of blocks & interconnections at all hierarchy levels Libraries of graphic symbols –R–R–R–Ready – made primitives & functional blocks design

16. Libraries in Quartus II Prim –B–B–B–Basic Fbs Mf Mega_lpm Edif Own libs from self-created symbols

17. CAD Logic simulator –To verify behavior & timing of each hierarchy blocks / complete circuit –Apply a set of inputs to determine the outputs

18. Hardware Description Language Important to design complex circuits Similar to other programming languages Describe hardware structures & behavior

19. Power of HDL Used to represent –Schematic information –Boolean equations –Truth tables Can use hierarchical design approach –High – level description can be partitioned into lower – level descriptions

20. Logic synthesis –An HDL description written at an intermediate level called Register Transfer Language (RTL) Register Transfer Language (RTL) –It can be converted into interconnection of primitive components that forms the circuit HDLs are portable across CAD design tools Power of HDL

21. HDL Languages VHDL –Very High – Speed ICs –Developed by DoD, US –IEEE standard Verilog HDL –IEEE standard AHDL

22. What have been discussed Design hierarchy –Top – down –Bottom – up CAD (Computer Aided Design) HDL (Hardware Description Language) Logic synthesis

23. Analysis Procedure Analysis –To determine the function of a circuit Derive Boolean equation Derive Boolean equation Derive truth table Derive truth table

24. Analyze this logic diagram T1 T3 T2 T4 T5

25. Boolean Equation T1 = BC T2 = AB T3 = A + T1 = A + BC T4 = T2 + D = AB + D T5 = AB + D F1 = T3 + T4 = (A+BC) + (AB + D) F2 = T5 = AB + D

26. Analyze this Binary Adder R1 R2 R3 C

27. Truth Table XYZCCR1R2R3S

28. XYZ 000 001 010 011 100 101 110 111CCR1R2R3S010000 010111 010111 100100 010111 100100 100100 101101

29. Logic Simulation A fast and accurate method of analyzing a combinational circuit Using simulator software Results : –Waveforms –A complete truth table –Part of a truth table

30. Logic Simulation How is the circuit described in the software ? –Schematics –HDL

31. Schematic for Binary Adder in Xilinx

32. Waveforms for Binary Adder 0000000000 0110101101 1111111111

33. Truth Table XYZ 000 001 010 011 100 101 110 111CCR1R2R3S010000 010111 010111 100100 010111 100100 100100 101101

34. Simulation in Max Plus II

35. Waveforms in MaxPlus II

36. Point to ponder…. Why do we compare the simulation results vs the theoretical results?

37. Design Procedure Given : Specifications of the problem 1. Determine input & output 2. Derive truth table 3. Obtain Boolean equation (K-map) 4. Draw schematics 5. Verify design

38. Design of BCD to Excess – 3 Code Converter Specifications : Input in decimal numbers, 0 – 9, in binary form Output is excess – 3 code e.g. –Input: Decimal = 5 (101) –Output: Excess – 3 code = 5 + 3 = 8 (1000)

39. BCD  Excess – 3 Step 1: Determine input & output Input : 0 to 9, 4 – bit binary code  A, B, C, D Output : 3 to 12, 4 – bit binary code  W, X, Y, Z

40. BCD  Excess – 3 Step 2 : Derive Truth Table Dec 0 1 2 3 4 5 6 7 8 9ABCD0000 0001 0010 0011 0100 0101 0110 0111 1000 1001WXYZ0011 0100 0101 0110 0111 1000 1001 1010 1011 1100Dec3 4 5 6 7 8 9 10 11 12

41. BCD  Excess – 3 Step 3 : Boolean Equation W = A + BC + BD W = A + BC + BD X = BC + BD + BCD X = BC + BD + BCD Y = CD + CD = Y = CD + CD = Z= D Z= D

42. BCD  Excess – 3 Step 4 : Schematic diagram

43. BCD  Excess – 3 Step 4 : Schematic diagram

44. BCD  Excess – 3 Step 5 : Verify that schematic diagram agrees with truth table

45. Design of BCD to 7 – segment decoder Specifications : Input in decimal numbers, 0 – 9, in binary form 7 Outputs – to display input number

46. 7 – segment Display

47. BCD to 7 –segment decoder Step 1 : Determine input & output

48. BCD to 7 – segment decoder Step 2 : Derive Truth Table ABCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 All other inputs abcdefg1111110 0110000 1101101 1111001 0110011 1011011 1011111 1110000 1111111 1111011 0000000

49. Exercise A traffic light system has the following specifications for a part of its controller. There are 3 parallel lanes, each with its own red / green light. One of these lanes, the priority lane, is given priority for a green light over the other 2 lanes. On the other hand, an alternating scheme is used for the other 2 lanes, which are left and right lane. Design the circuit that determines which light is to be green at a particular time. The specifications for the controller are as follows :

50. Exercise Inputs : PS – Priority Lane Sensor ( car present = 1; car absent = 0 ) LS – Left Lane Sensor ( car present = 1; car absent = 0 ) RS – Right Lane Sensor ( car present = 1; car absent = 0 ) AS – Alternating Signal ( select left = 1; select right = 0 ) Outputs : PL – Priority Lane Light ( green = 1; red = 0 ) LL – Left Lane Light ( green = 1; red = 0 ) RL – Right Lane Light ( green = 1; red = 0 )

51. Exercise 1. If there is a car in the priority lane, PL = 1. 2. If there are no cars in the priority lane and the right lane, and there is a car in the left lane, LL = 1. 3. If there are no cars in the priority lane and in the left lane, and there is a car in the right lane, RL = 1. 4. If there is no car in the priority lane, there are cars in both the left and right lanes, and AS = 1, then LL = 1. 5. If there is no car in the priority lane, there are cars in both the left and right lanes, and AS = 0, then RL = 1. 6. If any PL, LL or RL is not specified to be 1 above, then it has value 0.

52. Propagation Delay

53. PROPAGATION DELAY Definition:  The delay time for the change in value of a signal to propagate from input to output. input output

54. delaY vs sPeeD “Operating Speed” is inversely proportional to the longest propagation delay.

55. Propagation Delay Parameters Propagation delay is the time for a change on an input of a gate to propagate to the output. Delay is usually measured at the 50% point with respect to the H and L output voltage levels. High-to-low (t PHL ) and low-to-high (t PLH ) output signal changes may have different propagation delays. High-to-low (HL) and low-to-high (LH) transitions are defined with respect to the output, not the input. An HL input transition causes: –an LH output transition if the gate inverts and –an HL output transition if the gate does not invert.

56. Propagation Delay Parameters … t PHL The high-to-low propagation time the delay measured from the reference voltage on the input voltage, IN, to the reference voltage on the output voltage, OUT, with the output voltage going from H to L. the delay measured from the reference voltage on the input voltage, IN, to the reference voltage on the output voltage, OUT, with the output voltage going from H to L.

57. Propagation Delay Measurements for an Inverter Propagation delays measured at the midpoint between the L and H values

58. Propagation Delay Parameters … t PLH The low-to-high propagation time the delay measured from the reference voltage on the input voltage, IN, to the reference voltage on the output voltage, OUT, with the output voltage going from L to H. the delay measured from the reference voltage on the input voltage, IN, to the reference voltage on the output voltage, OUT, with the output voltage going from L to H.

59. Propagation Delay Measurements for an Inverter Propagation delays measured at the midpoint between the L and H values

60. Propagation Delay Parameters … t PD The propagation delay time the maximum of the two delays; the maximum of the two delays; t PD = (t PLH and t PHL )

61. Propagation Delay Measurement Exercise Find t PHL, t PLH and t pd for the signals given IN (volts) OUT (volts) t (ns) 1.0 ns per division

62. ProGrammaBle loGic

63. Implementation Technology Programmable Implementation Technologies – Read-Only Memories, Programmable Logic Arrays, Programmable Array Logic Technology mapping to programmable logic devices Technology mapping to programmable logic devices

64. Why Programmable Logic? Facts: –It is most economical to produce an IC in large volumes –Many designs required only small volumes of ICs Need an IC that can be: –Produced in large volumes –Handle many designs required in small volumes A programmable logic part can be: – made in large volumes – programmed to implement large numbers of different low-volume designs

65. Programmable Logic - Additional Advantages Many programmable logic devices are field- programmable, i. e., can be programmed outside of the manufacturing environment Most programmable logic devices are erasable and reprogrammable. –Allows “updating” a device or correction of errors –Allows reuse the device for a different design - the ultimate in re-usability! –Ideal for course laboratories Programmable logic devices can be used to prototype design that will be implemented for sale in regular ICs. –Complete Intel Pentium designs were actually prototype with specialized systems based on large numbers of VLSI programmable devices!

66. Technology Characteristics Permanent - Cannot be erased and reprogrammed Mask programming FuseAntifuseReprogrammable –Volatile - Programming lost if chip power lost Single-bit storage element –Non-Volatile Erasable Electrically erasable Flash (as in Flash Memory) –Build lookup tables Storage elements (as in a memory) –Transistor Switching Control Stored charge on a floating transistor gate –Erasable –Electrically erasable –Flash (as in Flash Memory) Storage elements (as in a memory)

67. Programmable Configurations Read Only Memory (ROM) - a fixed array of AND gates and a programmable array of OR gates Programmable Array Logic (PAL)  - a programmable array of AND gates feeding a fixed array of OR gates. Programmable Logic Array (PLA) - a programmable array of AND gates feeding a programmable array of OR gates. Complex Programmable Logic Device (CPLD) / Field- Programmable Gate Array (FPGA)

68. The End