1. 1 CSE370, Lecture 8 Lecture 8 u Logistics n Midterm 1 week from today in class. Closed book/closed notes n Sample midterm linked in on calendar n Review session Thursday Jan 29, 4:30. Location TBA u Last lecture n Verilog u Last last lecture n K-map examples n K-map high dimension example n Don’t cares u Today n Don’t care (review) n POS minimization with K-map n Design examples with K-map n "Switching-network" logic blocks (multiplexers/demultiplexers)

2. 2 CSE370, Lecture 8 The “WHY” slide u Don’t cares n Sometimes the logic output doesn’t matter. When we don’t care if the output is 0 or 1, rather than assigning random outputs, it is best to denote it as “Don’t care.” If you learn how to use the “don’t care’s”, you will be able to build even more efficient circuits than without them. u Design examples with K-map n Doing K-map is fun, but when it is combined with an actual design problem you will see how k-map fits into the whole scheme of logic design. u “Switching network” blocks (multiplexers) n Routing method for data paths helps to structure logic design

3. 3 CSE370, Lecture 8 Revisit Don’t cares example: Truth table for a BCD increment-by-1 ABCDWX YZ 00000001 00010010 00100011 00110100 01000101 01010110 01100111 01111000 10001001 10010000 1010XXXX 1011XXXX 1100XXXX 1101XXXX 1110XXXX 1111XXXX INPUTS OUTPUTS Function F computes the next number in a BCD sequence If the input is 0010 2, the output is 0011 2 BCD encodes decimal digits 0–9 as 0000 2 –1001 2 Don’t care about binary numbers 1010 2 –1111 2

4. 4 CSE370, Lecture 8 Notation u Don't cares in canonical forms n Three distinct logical sets: {on}, {off}, {don’t care} u Canonical representations of a BCD increment-by-1 n Minterm expansion íW = m7+m8+d10+d11+d12+d13+d14+d15 =  m(7,8) + d(10,11,12,13,14,15) n Maxterm expansion íW = M0M1M2M3M4M5M6M9D10D11D12D13D14D15 =  M(0,1,2,3,4,5,6,9) D(10,11,12,13,14,15) u In K-maps, can treat ‘don't cares’ as 0s or 1s n Depending on which is more advantageous

5. 5 CSE370, Lecture 8 Example: with don’t cares  F(A,B,C,D) =  m(1,3,5,7,9) + d(6,12,13) n F = A'D + B'C'Dwithout using don't cares n F = A'D + C'Dusing don't cares 00X011X111000X0000X011X111000X00 AB CD A B D 00011110 00 01 11 10 C Assign X == "1"  allows a 2-cube rather than a 1-cube

6. 6 CSE370, Lecture 8 POS minimization using k-maps u Using k-maps for POS minimization n Encircle the zeros in the map n Interpret indices complementary to SOP form 10010100111111111001010011111111 AB CD A B D 00011110 00 01 11 10 C F = (B’+C+D)(B+C+D’)(A’+B’+C) Same idea as the Truth Table

7. 7 CSE370, Lecture 8 Design example: a two-bit comparator block diagram truth table Need a 4 -variable Karnaugh map for each of the 3 output functions LT EQ GT ABCDLTEQGT 0000010 01100 10100 11100 0100001 01010 10100 11100 1000001 01001 10010 11100 1100001 01001 10001 11010 AB CD ABCDABCD

8. 8 CSE370, Lecture 8 01110011000000100111001100000010 10000100001000011000010000100001 00001000110111000000100011011100 Design example: a two-bit comparator (con’t) LT = A'B'D+A'C+B'CD D AB CD A 00011110 00 01 11 10 C B D AB CD A 000111 10 00 01 11 10 C B D AB CD A 00011110 00 01 11 10 C B GT = BC'D'+AC'+ABD' EQ = A'B'C'D'+A'BC'D+ABCD+AB'CD' = (A xnor C)(B xnor D) K-map for EQK-map for LTK-map for GT

9. 9 CSE370, Lecture 8 u Two ways to implement EQ: Option 1: EQ = A'B'C'D'+A'BC'D+ABCD+AB'CD‘ 5 gates but they require lots of inputs Option 2 EQ = (A xnor C) (B xnor D) XNOR is constructed from 3 simple gates 7 gates but they all have 2 inputs each Design example: a two-bit comparator (con’t)

10. 10 CSE370, Lecture 8 Design example: a two-bit comparator (con’t) Circuit schematics

11. 11 CSE370, Lecture 8 Design example: BCD increment by 1 I8I4I2I1O8O4O2O1 00000001 00010010 00100011 00110100 01000101 01010110 01100111 01111000 10001001 10010000 1010XXXX 1011XXXX 1100XXXX 1101XXXX 1110XXXX 1111XXXX O1 O2 O4 O8 I1 I2 I4 I8 block diagram truth table Need a 4 -variable Karnaugh map for each of the 4 output functions

12. 12 CSE370, Lecture 8 O8O8 O4O4 O2O2 O1O1 00X100X001XX00XX00X100X001XX00XX I1I1 I8I8 I2I2 I4I4 00X011X000XX11XX00X011X000XX11XX 11X100X000XX11XX11X100X000XX11XX I1I1 I8I8 I2I2 I4I4 I1I1 I8I8 I2I2 I4I4 I1I1 I8I8 I2I2 I4I4 01X001X010XX01XX01X001X010XX01XX We greatly simplify the logic by using the don’t cares O 8 = I 4 I 2 I 1 + I 8 I 1 ‘ O 4 = I 4 I 2 ' + I 4 I 1 ' + I 4 'I 2 I 1 O 2 = I 8 'I 2 'I 1 + I 2 I 1 ‘ O 1 = I 1 ' Design example: BCD increment by 1 (con’t)

13. 13 CSE370, Lecture 8 Design example: a two-bit multiplier A2A1B2B1P8P4P2P1 00000000 010000 100000 110000 01000000 010001 100010 110011 10000000 010010 100100 110110 11000000 010011 100110 111001 P1 P2 P4 P8 A1 A2 B1 B2 block diagram truth table 9 Need a 4 -variable Karnaugh map for each of the 4 output functions

14. Two-bit multiplier (cont'd) 00000000000100110000000000010011 B1 A2A1 B2B1 A2 00011110 00 01 11 10 B2 A1 00000110011000000000011001100000 B1 A2A1 B2B1 A2 00011110 00 01 11 10 B2 A1 00000000001000000000000000100000 B1 A2A1 B2B1 A2 00011110 00 01 11 10 B2 A1 00000011010101100000001101010110 B1 A2A1 B2B1 A2 00011110 00 01 11 10 B2 A1 P8=A2A1B2B1P8=A2A1B2B1 P 2 =A 2 'A 1 B 2 +A 1 B 2 B 1 ' +A 2 B 2 'B 1 +A 2 A 1 'B 1 P 4 =A 2 B 2 B 1 ' +A 2 A 1 'B 2 P1=A1B1P1=A1B1

15. 15 CSE370, Lecture 8 Switching-network logic blocks u Multiplexer (MUX) n Routes one of many inputs to a single output n Also called a selector u Demultiplexer (DEMUX) n Routes a single input to one of many outputs n Also called a decoder multiplexerdemultiplexer control We construct these devices from: logic gates networks of transistor switches

16. 16 CSE370, Lecture 8 Multiplexers u Basic concept n 2 n data inputs; n control inputs ("selects"); 1 output n Connects one of 2 n inputs to the output n “Selects” decide which input connects to output n Two alternative truth-tables: Functional and Logical Example: A 2:1 Mux Z = SIn 1 + S'In o Functional truth table SZ 0In 0 1In 1 In 1 In 0 SZ 0000 0010 0101 0110 1000 1011 1101 1111 Logical truth table I0I0 S I1I1 Z

17. 17 CSE370, Lecture 8 Multiplexers (con't) u 2:1 mux:Z = S 0 'In 0 + S 0 In 1 u 4:1 mux:Z = S 1 'S 0 'In 0 + S 1 'S 0 In 1 + S 1 S 0 'In 2 + S 1 S 0 In 3 u 8:1 mux:Z = S 2 'S 1 'S 0 'In 0 + S 2 'S 1 'S 0 In 1 +... I0I1I2I3I4I5I6I7I0I1I2I3I4I5I6I7 S 2 S 1 S 0 8:1 mux Z I0I1I2I3I0I1I2I3 S 1 S 0 4:1 mux Z I0I1I0I1 S0S0 2:1 mux Z

18. 18 CSE370, Lecture 8 Logic-gate implementation of multiplexers 2:1 mux4:1 mux I0I1I2I3I0I1I2I3 S 1 S 0 I0I0 S I1I1 Z Z Z

19. 19 CSE370, Lecture 8 Cascading multiplexers u Can form large multiplexers from smaller ones n Many implementation options Z 4:1 mux S2S2 2:1 mux I4I5I6I7I4I5I6I7 S 1 S 0 4:1 mux S0S0 Z S 2 S 1 4:1 mux 2:1 mux I4I5I4I5 I2I3I2I3 I0I1I0I1 I6I7I6I7 8:1 mux I0I1I2I3I0I1I2I3

20. 20 CSE370, Lecture 8 Multiplexers as general-purpose logic u A 2 n :1 mux can implement any function of n variables n A lookup table n A 2 n – 1 :1 mux also can implement any function of n variables u Example: F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB(0) + AB(1) ABCF00010010010101101000101011011111ABCF00010010010101101000101011011111 C' C' 0 1 0123456701234567 1010001110100011 S2 8:1 MUX S1S0 F A B C S1S0 F 01230123 4:1 MUX C' C' 0 1 A B

21. 21 CSE370, Lecture 8 10111000110101101011100011010110 Multiplexers as general-purpose logic u Implementing a 2 n-1 :1 mux as a function of n variables n (n-1) mux control variables S 0 – S n–2 n One data variable S n-1 n Four possible values for each data input: 0, 1, S n-1, S n-1 ' n Example: F(A,B,C,D) implemented using an 8:1 mux Choose A,B,C as control variables Choose D as a data variable 0123456701234567 1 D 0 1 D' D D' D' A 8:1 MUX B C F D AB CD A 00011110 00 01 11 10 C B S2 S1 S0

22. 22 CSE370, Lecture 8 Demultiplexers (DEMUX) u Next class