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Registers ECEn/CS 224
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Called a serial-in, parallel-out shift register (SIPO)
A Shift Register Q3 Q2 Q1 Q0 D Q D Q D Q D Q Serial-In CLK CLK CLK CLK Called a serial-in, parallel-out shift register (SIPO) ECEn/CS 224
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A 4-Bit Register D Q D3 Q3 CLK D Q D2 Q2 D Q D Q CLK D Q CLK D1 Q1 CLK
ECEn/CS 224
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SIPO (Serial-In/Parallel-Out)
Q3 Q2 Q1 Q0 D Q D Q D Q D Q Serial-In CLK CLK CLK CLK ECEn/CS 224
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SISO (Serial-In/Serial-Out)
D Q D Q D Q D Q Serial-Out Serial-In CLK CLK CLK CLK ECEn/CS 224
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PIPO (Parallel-In, Parallel-Out)
D Q D Q 4 4 CLK ECEn/CS 224
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How to Make Any of These Loadable?
D Q D Q D Q D Q 4 4 4 4 CLK CLK LOAD This register loads on every clock cycle. How to make it load when told to? This is an incorrect solution Why? ECEn/CS 224
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Gated Clocking Is A Bad Thing To Do…
D Q CLK D Q LOAD GatedClock tAND The flip flop gets its clock signal late CLK LOAD GatedClock ECEn/CS 224
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Gated Clocking Different flip flops load at different times
A form of clock skew Makes doing timing analysis more difficult Can lead to circuits which run more slowly Can lead to circuits which fail at any clock rate ECEn/CS 224
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Value that should be loaded into FFB (‘1’)
D Q QA D Q Q FFA FFB LOAD GatedClock CLK CLK Value that should be loaded into FFB (‘1’) tCLK-Q tAND Value that gets loaded into FFB (‘0’) CLK QA LOAD GatedClock ECEn/CS 224
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Value that should be loaded into FFB (‘1’)
D Q QA D Q Q FFA FFB If tCLK-Q < tAND: FFB loads wrong value LOAD GatedClock CLK CLK Value that should be loaded into FFB (‘1’) tCLK-Q tAND Value that gets loaded into FFB (‘0’) CLK QA LOAD GatedClock ECEn/CS 224
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Globally Synchronous Design
One global clock All registers load on that clock’s edge Control over loading done via input forming logic (IFL) Simplifies timing analysis and requirements Makes it possible for novices to design large, functioning circuits Multi-clock circuits next semester’s topic ECEn/CS 224
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The Correct Way To Make A Loadable Register (1-Bit)
1 D Q Q DIN LOAD CLK When LOAD=‘0’, FF loads old value When LOAD=‘1’, FF loads DIN ECEn/CS 224
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A Loadable Parallel-In, Parallel-Out Register
1 D Q Q(3:0) 4 4 DIN(3:0) 4 LOAD CLK PIPO ? ECEn/CS 224
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A Loadable Parallel-In, Serial-Out Register (PISO)
Serial-In 1 D Q 1 D Q 1 D Q Serial-Out LOAD/SHIFT# CLK LOAD/SHIFT# CLK LOAD/SHIFT# CLK D2 D1 D0 When LOAD/SHIFT#=‘1’, register loads D2-D0 When LOAD/SHIFT#=‘0’, register shifts right This register is always either loading or shifting… ECEn/CS 224
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MUX for Register Control
Loadable register concept can be generalized Provide any combination of inputs to register ECEn/CS 224
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A SISO With An Enable Input
1 D Q 1 D Q 1 D Q Serial-Out Serial-In ENABLE ENABLE ENABLE CLK CLK CLK Combination of loadable register with shift register… When ENABLE=‘0’, register doesn’t shift (loads old value) When ENABLE=‘1’, register shifts ECEn/CS 224
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A Bidirectional Shift Register
D Q Q2 1 CLK UP/DOWN# Top-In Q1 D Q Q1 1 CLK UP/DOWN# Q2 Q0 Q1 D Q Q0 1 CLK UP/DOWN# Bottom-In ECEn/CS 224
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Uses of Shift Registers
Collecting serial input data into a parallel word Shifting out bits of a word Delaying a serial stream by some # of cycles ECEn/CS 224
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(when you have a MUX and some flip flops)
A Clearable Counter Q 4 Q+1 D Q 4 Q 4 4 4 Q 4 2 CLK CLR INC From there to here, from here to there, interesting circuits are everywhere… (when you have a MUX and some flip flops) ECEn/CS 224
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How about an up/down counter + bi-directional shift register design?
Q-1 1 D Q Q 4 4 Q+1 CLK UP/DN# How about an up/down counter + bi-directional shift register design? ECEn/CS 224
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Up/Down Counter + Bi-Directional Shift Register
Q+1 4 Q-1 D Q 4 Q Q<<1 4 4 4 Q>>1 4 2 CLK Control ECEn/CS 224
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An Accumulator Values to be added are placed on A input, one per cycle. Register accumulates their sum. Version A Version B A + A + 1 D Q 1 D Q 4 Q Q 4 4 4 4 4 CLR CLR CLK CLK This one loads 0 when CLR=‘1’ This one loads A+0 when CLR=‘1’ Both work, they just have different timings… ECEn/CS 224
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Small memories holding multiple words of data
Register Files Small memories holding multiple words of data ECEn/CS 224
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Typical Register File DataIn n clk regWE RegFile Addr m n DataOut
ECEn/CS 224
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Typical Register File Data to be written to register file DataIn n clk
regWE RegFile Addr m n DataOut ECEn/CS 224
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Typical Register File Data to be written to register file DataIn n clk
regWE RegFile Addr m n DataOut Data that is read from register file ECEn/CS 224
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Typical Register File Data to be written to register file DataIn n clk
regWE RegFile Addr m Address that reads and writes are for n DataOut Data that is read from register file ECEn/CS 224
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Typical Register File Data to be written to register file DataIn n clk
regWE This register will hold 2m words, each n bits wide RegFile Addr m Address that reads and writes are for n DataOut Data that is read from register file ECEn/CS 224
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Typical Register File Data to be written to register file DataIn n clk
regWE Controls whether reading or writing This register will hold 2m words, each n bits wide RegFile Addr m Address that reads and writes are for n DataOut Data that is read from register file ECEn/CS 224
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Typical Register File Reads are asynchronous (combinational)
Writes occur on the clock edge. Data to be written to register file DataIn n clk regWE Controls whether reading or writing This register will hold 2m words, each n bits wide RegFile Addr m Address that reads and writes are for n DataOut Data that is read from register file ECEn/CS 224
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Building a Register File
Write Decoder Reg0 n Reg1 n Reg2 n Reg3 n Register write signals 8:1 MUX DataOut Reg4 n n Reg5 n Reg6 n Reg7 n m=3 n regWE DataIn clk Addr ECEn/CS 224
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Building a Register File
Asynchronous read: just a MUX Write Decoder Reg0 n Reg1 n Reg2 n Reg3 n Register write signals 8:1 MUX DataOut Reg4 n n Reg5 n Reg6 n Reg7 n m=3 n regWE DataIn clk Addr ECEn/CS 224
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Building a Register File
Loadable registers Asynchronous read: just a MUX Write Decoder Reg0 n Reg1 n Reg2 n Reg3 n Register write signals 8:1 MUX DataOut Reg4 n n Reg5 n Reg6 n Reg7 n m=3 n regWE DataIn clk Addr ECEn/CS 224
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Building a Register File
Loadable registers Asynchronous read: just a MUX Write Decoder Reg0 n 3:8 Decoder with enable Reg1 n Reg2 n Reg3 n Register write signals 8:1 MUX DataOut Reg4 n n Reg5 n Reg6 n Reg7 n m=3 n regWE DataIn clk Addr ECEn/CS 224
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Register write signals
Loadable Register Reg0 Reg1 Reg2 Reg3 Reg4 Reg5 Reg6 Reg7 Register write signals DataIn clk n Regk clk n Load D Q DataIn regWEk Qk ECEn/CS 224
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Write Decoder Write Decoder 3:8 Register write signals Decoder
Addr m=3 regWE Register write signals Write Decoder Addr regWE Register write signals m=3 ECEn/CS 224
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Multi-Ported Register File
One write port, one read port. Different write and read addresses Can be reading from one location on same cycle you write to another location Write Decoder Reg0 Reg1 Reg2 Reg3 Register write signals DataOut 8:1 MUX Reg4 Reg5 Reg6 Reg7 WAddr WE DataIn clk RAddr ECEn/CS 224
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Multi-Ported Register File
Write Decoder Reg0 One write port Two read ports Can be reading from two locations on same cycle you write to another location Useful for Microprocessor design Reg1 Reg2 Reg3 Register write signals DataOut1 Reg4 8:1 MUX Reg5 DataOut2 Reg6 Reg7 WAddr WE DataIn clk Raddr2 RAddr1 ECEn/CS 224
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Memories vs. Register Files
Random Access Memory (RAM) is similar to a register file Stores many multi-bit words for reading/writing RAM usually only single-ported RAM usually much, much larger Mbytes instead of bytes RAM implementation conceptually the same as register file Transistor-level implementation different due to size/usage characteristics RAM design beyond the scope of this class ECEn/CS 224
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