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Chapter4: Combinational Logic Part 4 Originally By Reham S. Al-Majed Imam Muhammad Bin Saud University
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Outline 2 Multiplexer Definition Examples MUX and Decoder. MUX Expansion. Circuit Implementation with MUX DeMultiplexer
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Definition 3 It is a cc that select binary information from one of many input lines to single output line. The selection of input line depends on selection lines. Its ab consists of: Inputs lines = 2 n Output line = 1 Selectors (depends on number of inputs) = n An active high or active low enable input (not all multiplexers have it) I 2 n -1 I0I0 MUX................ S0S0 S n-1 2 n Inputs lines n selection lines
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Definition 4 I0I0 I1I1 I2I2 I3I3 00 MUX Y=I 0 I0I0 I1I1 I2I2 I3I3 10 MUX Y=I 1 I0I0 I1I1 I2I2 I3I3 01 MUX Y= I 2 I0I0 I1I1 I2I2 I3I3 11 MUX Y=I 3
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Example 1 5 Design a 2-to-1 multiplexer: 1. 2 data inputs (I 0,I 1 ), 1 select input S, and 1 output (Y) 2. Truth table: SI1I1 I0I0 Y 000I0=0I0=0 001I0=1I0=1 010I0=0I0=0 011I0=1I0=1 100I1=0I1=0 101I1=0I1=0 110I1=1I1=1 111I1=1I1=1 SY 0 I0I0 1 I1I1
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Example 1 (cont.) 6 3. Simplification: Y = S’ I 0 + S I 1 3. Diagram: 11 11 S I0I0 I1I1
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Example 2 7 Design 4-to1 MUX: There are four data inputs two selection inputs S 1,S 0. The input selected to be passed to the output depends on the minterm of the input. Y = S 1 ’S 0 ’I 0 + S 1 ’S 0 I 1 + S 1 S 0 ’I 2 + S 1 S 0 I 3 mintermS1S1 S0S0 Y m0m0 00 I0I0 m1m1 01 I1I1 m2m2 10 I2I2 m3m3 11 I3I3 m1m1 m2m2 m3m3 m0m0
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Multiplexer and Decoder 8 The AND gates and inverters in the MUX resemble a decoder circuit. They decode selection input lines. 2 n -to-1 line multiplexer is constructed from n-to-2 n decoder. Example: 4-to-1 MUX constructed from 2-to-4 decoder
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Multiplexer Expansion 9 Design a 4-to-1 MUX with 2-to-1 MUXes only. 4-to-1 has 4 data input, 2 selection input, and 1 output. 2-to-1 has 2 data input, 1 selection input, and 1 output. S1S1 S0S0 Y 00 D0D0 01 D1D1 10 D2D2 11 D3D3 D0D0 D1D1 MUX D2D2 D3D3 Y S0S0 S1S1 I0I0 I1I1 I0I0 I1I1 I0I0 I1I1
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CC Implementation with MUX 10 Given a function of n-variables MUXex can be used to implement this function. This can be accomplished in one of 2 ways: Using a Mux with n-select inputs n variables need to be connected to n select inputs. Minterms of a function are generated according to select inputs. Individual minterm can be selected by the data inputs proper assignment of the data inputs (D i ∈ {0, 1}). Using a Mux with n-1 select inputs (more efficient) Find truth table. The first n-1 variables in table are connected to selection inputs of MUX (which order ?). For each combination of selection variables, evaluate output as function of the remaining variable (d) This remaining variable (d) is then used for data inputs which can be 0,1,d,d’.
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Example 1 11 Implement the function F(x,y,z) = ∑(1,2,6,7) using a Mux with n- select inputs. The function has 3 variables using 3-select inputs, we need a 8-to-1 MUX. 8-to-1 MUX x y z F 1 0 1 1 1 0 0 0 1 0 2 3 4 5 6 7
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Example 2 12 Implement the function F(x,y,z) = ∑(1,2,6,7) using a Mux with n-1 -select inputs. The function has 3 variables using 2-select inputs, we need a 4-to-1 MUX. 4-to-1 MUX x y F z z’ 0 1 0 1 3 2
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De-Multiplexer 13 It is a CC that performs the inverse operation of MUX. It has: 1 input 2 n outputs. n selection inputs to select outputs. Example: design 1-to-4 DeMUX 1-to-4 DeMUX A1A1 E A0A0 D0D0 D1D1 D2D2 D3D3 A1A1 A0A0 D0D0 D1D1 D2D2 D3D3 00E000 010E00 1000E0 11000E
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Reading 14 4.1 4.2 4.3 4.4 4.5 EXCEPT: Carry propagation. 4.6 Reading Assignment. 4.7 Reading Assignment. 4.9 4.10 4.11
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