1. CSC Ops/DPG meeting, 05-Oct-2011 Hauser1 ALCT boards for ME4/2 etc.

2. CSC Ops/DPG meeting, 05-Oct-2011 Hauser2 ME4/2 electronics boards on-chamber Peripheral Crates FED Crates Need for ME4/2 Already have

3. CSC Ops/DPG meeting, 05-Oct-2011 Hauser3 CSC system layout CSC CFEB ALCT 1 of 24 CFEB 1 of 2 LVDB LV Distribution Board FED Crate in USC55 1 of 5 Anode Front-end Board Cathode Front-end Board Anode LCT Board MPCMPC DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB CCBCCB CONTROLLERCONTROLLER Peripheral Crate on iron disk Slow Control Trigger-Timing-Control Muon Sector Receiver Lev-1 Trigger Trig Motherboard DAQ Motherboard Clock Control Board DDU Board Readout Data

4. CSC Ops/DPG meeting, 05-Oct-2011 Hauser4 ALCTs for ME4/2 - general plan One 384-channel board per chamber, so 80 needed Build new boards (Now have 29 spares, ~15 working) Tailwind: funding that expires Dec. 31, 2011(!) 3-month extension “likely”, but not guaranteed

5. CSC Ops/DPG meeting, 05-Oct-2011 Hauser5 ALCT384 board design Analog section: test pulse generator, AFEB power, ADCs, DACs (other side) Input signal connectors Delay/ buffer ASICs, 2:1 bus multiplexors (other side) 80 MHz SCSI outputs (to Trigger Motherboard (to Trigger Motherboard) Power, computer connectors Spartan XL Mezzanine card Trigger, DAQ logic Base board

6. CSC Ops/DPG meeting, 05-Oct-2011 Hauser6 New base boards Have original design files Schematic design Layout for board fabrication and assembly Plan to keep the same design Clock distribution is non-optimal, but acceptable Existing board works reliably

7. CSC Ops/DPG meeting, 05-Oct-2011 Hauser7 Base board progress Parts: All electronics and mechanical parts have been ordered, expect to receive all by mid-October Was non-trivial (some not in production, lead-free substitutions…) Delay ASICs will have to use “bin 4” 21-49 ns, versus existing ALCT384 “bin 7 and 8” 22-56 ns Timing changes by about 1-7ns (as delay code 0,1,2,..,15) Can adjust resistor values to reduce the difference Board fabrication By original vendor (Cirtech) All boards have been ordered, due Oct. 4-11

8. CSC Ops/DPG meeting, 05-Oct-2011 Hauser8 New ALCT384 mezzanine board Original design files in hand FPGA choices: Original Virtex-E (ca. 2001) Spartan-6

9. CSC Ops/DPG meeting, 05-Oct-2011 Hauser9 Spartan-6 comparison to Virtex-E XC6SLX150/fg900 package vs. XCV600E/fg680 Both 3.3v I/O, sufficient # pins (576 vs. 516) Price $230 vs. $735 Performance/capability: 92K vs. 9.6K look-up tables Speed 1.5-2.0x, maybe Power only ~0.2W quiescent, 0.49-1.15W active  Configuration from EPROM takes 212ms vs. 25ms vs. present 101ms for TMB, new ME1/1 TMBs 385 ms (8-bit)  Needs separate firmware files  Core voltage needs on-board conversion 1.8  1.2v Also need +2.5v for VCCaux

10. CSC Ops/DPG meeting, 05-Oct-2011 Hauser10 Performance of Spartan-6 10x logic capacity, ~2x speed Improvements needing study: More patterns point better to IP reduce n’s, halo, albedo etc. at trigger primitive level More patterns give better eta precision for CSC-TF Better trigger timing through use of trailing edges Could use in TMB ghost suppression Generally: high-luminosity “insurance”

11. CSC Ops/DPG meeting, 05-Oct-2011 Hauser11 Opportunity with Spartan-6 Cost per board ~$500 versus ~$1000 Virtex-E  Could build for ME4/2 and for ME1/1 Cost is $80K for ME4/2 for Virtex-E Cost is $80K for ME4/2 and ME1/1 for Spartan-6 Expected technical challenges greatest for ME1/1 (high rate) NB make ME1/1 replacement only in 2013 Concern: a new chip, what about SEU rate? Tests on Spartan-6 and Virtex-6 by Los Alamos, Xilinx engineers “Per-bit” error rate /100 About 10x more bits  0.1 the rate/chip as for Virtex-E

12. CSC Ops/DPG meeting, 05-Oct-2011 Hauser12 Spartan-6 mezzanine progress Firmware already ported, no issues Design: Fully compatible design Uses rad-hard regulators for 2.5v, 1.8v, 1.2v Added an ADC to read these voltages, also 3.3v (main) First pass schematics done Layout: First pass done

13. CSC Ops/DPG meeting, 05-Oct-2011 Hauser13 Near-term plans Finish Spartan-6 design and layout Expect by mid-Oct. Assemble ~5 pre-production boards Need to “requalify” assembly company Ask for quick turnaround Base boards ~mid-Nov? Spartan-6 boards ~early-Dec? Bring up the ALCT test setup in UCLA Last used ~2 years ago (by Farrell and u.g.’s) Move to full production after the pre- production cycle

14. CSC Ops/DPG meeting, 05-Oct-2011 Hauser14 Backup

15. CSC Ops/DPG meeting, 05-Oct-2011 Hauser15 CSC Muon Trigger Scheme

16. CSC Ops/DPG meeting, 05-Oct-2011 Hauser16 ALCT Testing Board

17. CSC Ops/DPG meeting, 05-Oct-2011 Hauser17 ALCT Production Testing Using 3 stationsUsing 3 stations 2 for testing2 for testing 1 for fixing1 for fixing Crew of 4 students testingCrew of 4 students testing 2 students helping Valeri Iatsura with fixing.2 students helping Valeri Iatsura with fixing. (from 2002)

18. CSC Ops/DPG meeting, 05-Oct-2011 Hauser18 ALCT Test Procedures Six main tests: 1.Slow control test suite (done for all versions) various DAC, ADC, current, voltage, temperature tests 2.Internal pattern test (test firmware done for –384 and -672) Set trigger data in delay ASIC, then clock to FPGA at full speed, check trigger decision 3.TMB and AFEB pulse tests (done for –384 and -672) check SCSI I/O at full speed using test board and check test pulsing with oscilloscope. 4.Single cable input test (done for –384 and -672) clock data out SCSI and then into AFEB input at full speed using special cable. 5.Semi-automatic delay ASIC test (done for –384, flaky for others) loop over various delay values and check progression of signal at delay ASIC outputs using oscilloscope 6.(6/2002 listed as “desirable”) Fully-automatic delay ASIC test load data into Test Board FIFOs, then run into FPGA using various delay ASIC settings, analyze data to derive timing. (from 2002)