1. DIGITAL SYSTEMS Read Only– and Random Access Memory ( ROM – RAM) 2.12.04 Rudolf Tracht and A.J. Han Vinck

2. content Read Only Memory –Structure Random Access Memory –SRAM –DRAM

3. Read Only Memory (ROM) Storage of bits in a structured way: –Two dimensional 2 n x b –Every address specifies a pre-programmed output 2 n addresses b-bits wide output

4. Content „non-volatile“ Non-volatile: Content stays on chip, even without power Several types: ROMmask ROMs content programmed by manufacturer PROMPROM: Programmable ROM. All bits are pre-programmed to be 1. Bits (specified by address location) can be set to be equal to 0 by customer EPROMEPROM „erasable PROM“: Ultraviolet light „resets“ all bits equal to 1 EEPROMEEPROM "electrically erasable PROM“: individual bits can be reset to 1. (application smart-cards)

5. Some ROM applications CPU primitive instruction set CD-ROM ROM for logic functions, it stores a truth table –Structured design methods: simplification is not needed –Standardized building block: all ROMs are manufactured in identical steps except for the final customization phase –Example: Simple pre-programmed multiplier

6. example Multiply 2 x 2 bit words: A*B = CA*B = C 00 00000010 000000 00 01000010 010010 00 10000010 100100 00 11000010 110110 01 00000011 000000 01 01000111 010011 01 10001011 100110 01 11001111 111001

7. 2 n × b ROM organization n address inputs specify 2 n unique data words decoder b - outputs ROM-array

8. Implementation with MOS To store a 1 at a location: connect row j line to column i line with a MOSFET To include a minterm to output: connect row j line to column i line with a transistor R invertor L L H H H L j i i decoder H L j L L L

9. basic 2 n x b ROM structures decoder select 1-out-of 2 m rows array select 1-out of 2 n-m words address CS OE m-bits n-m-bits 1 1 0 1 2 n-m x b bits wide Chip select Output enable - output enable when CS. NAND. OE = 0 multiplexer b bits

10. Column multiplex four 8 x 1 multiplexer

11. Cascading memory modules example 256 X 8 ROM using 256 X 4 parts:

12. F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' example Combinational logic implementation (two-level canonical form) using a ROM ABCABC F0 F1 F2 F3 8 x 4

13. RAM- write or read information 2 n x b RAM b-bits wide input n-bits wide address b-bits wide output control CS OE WE CS: Chip select OE: Output enable WE: Write enable

14. Content „Volatile“ Volatile: looses content after Power-loss –Random Access Memory (RAM): access time constant DRAMDRAM "dynamic" (high density, low speed) used in main memory SRAMSRAM "static" (low density, high speed) used in CPU register file

15. 2D Memory Architecture A0A0 Row Decoder A1A1 A j-1 bit line word line storage (RAM) cell Row Address Column Address AjAj A j+1 A k-1 Read/Write Circuits Column Decoder 2 k-j m2 j Input/Output (m bits) selects appropriate word from memory row

16. Typical parallel DRAM organization 256Kb 0 1 7 512 rows 512 columns 2Mbit DRAM: 256K x 8bits = 2 18 x 8bits = 2 9 rows x 2 9 columns x 8 bits

17. AS7C4096

18. Internal structure of a 1x2 static RAM in1in0 D Q C in sel wr in out sel wr in out sel wr in out sel wr in out sel wr 1 x 2 decoder out1out0 WE CS OE 1 1 0 WE CS OE 1 1 0 latch open 0 1 0 latch closed 0 1 1 read content sel = 1 makes output available

19. Bidirectional bus structure in1 in0 D Q C in sel wr in out sel wr in out sel wr in out sel wr in out sel wr 1 x 2 decoder out1out0 WE CS OE 1 1 0 WE CS OE 1 1 0 latch open 0 1 0 latch closed 0 1 1 read content 1 1 1 latch closed * 0 * latch closed sel = 1 makes output available

20. Static RAM (SRAM) Read: Make word line H sense value on bit lines Write: Make word line H put values to Bit and !Bit flip-flop stays in stable state when word line  L !Bit = NOT(Bit) 6 MOSFETS  low density  higher cost/bit, but fast

21. Dynamic RAM (DRAM) Read: - make word line H, - sense voltage on bit line (destroys saved value, i.e. content must be written back) Write: - make word line H - put new value on bit line - make word line L ( freeze the capacitor load ) Refresh cycles are needed for the whole memory to restore the content! (do dummy read) Small cell  high density  lower speed  more difficult to produce

22. memory access Hardware Registers (CPU) Random Access: access time is the same for all locations –SRAM: Static Random Access Memory Low density, high power, expensive, fast Static: content will last “forever”(until no power) –DRAM: Dynamic Random Access Memory High density, low power, cheap, slow Dynamic: need to be “refreshed” regularly “Not-so-random” Access Technology: –Access time varies from location to location and from time to time –Examples: Disk, CDROM, DRAM page-mode access Sequential Access Technology: access time linear in location (e.g.,Tape) speed size

23. DRAM Generation ‘84 ‘87 ‘90‘93‘96‘99 1 Mb 4 Mb 16 Mb 64 Mb 256 Mb1 Gb 5585130200300450 304772110165250 28.8411.14.261.640.610.23 (from Kazuhiro Sakashita, Mitsubishi) DRAM over time 1st Gen. Sample Memory Size Die Size (mm 2 ) Memory Area (mm 2 ) Memory Cell Area (µm 2 )

24. trends CapacitySpeed (latency) Logic:2x in 3 years2x in 3 years DRAM:4x in 3 years2x in 10 years Disk:4x in 3 years2x in 10 years

25. µProc 60%/yr. (2X/1.5yr) DRAM 9%/yr. (2X/10 yrs) 1 10 100 1000 19801981198319841985198619871988198919901991199219931994199519961997199819992000 DRAM CPU 1982 Processor-Memory Performance Gap: (grows 50% / year) Performance Processor-DRAM Memory Gap (speed)

26. Page Mode/EDO RAM Normal RAM drives many bits (row) out of array, selects few to output. Adding latch at row outputs allows us to save an entire row of the RAM Later accesses to the RAM can eliminate the row access time, just need column access time Most common in DRAM, page- mode SRAMs also exist