1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Design and architecture Adders: –Carry Lookahead Adder (CLA) Fast Large Area (power) –Carry Save Adder (CSA) Fast Result is not binary Multiplier: Booth-2, Tree-Accumulator (5-levels cascaded CSA and one CLA)

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Synthesis Carry-Lookahead-Adders Carry-Save-Adders Implement Booth-2 Algorithm HDL Synthesis Estimates Frequency f 125 Mhz (7.974ns) Area A (# of LUT-FF Pairs) 388 Registers R (# of LUT-FF Pairs) 3384 # Pipeline Stages1 Metric1.7

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 Physical Synthesis Carry-Lookahead-Adders Carry-Save-Adders Implement Booth-2 Algorithm Synthesis Estimates Frequency f 100 Mhz (9.922ns) Area A (# of LUT-FF Pairs) 388 Registers R (# of LUT-FF Pairs) 2887 # Pipeline Stages1 Metric0.89

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Simulation Results

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Synthesis Results

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 In All 1.Observations: –Further optimization is still possible –Further footprint reduction requires a more complex wiring scheme –Complex Tree-Adder algorithms have an increasingly steeper learning curve 2.Discuss results –Constraints were met (barely). –Fast Adder => More Area (Power!) –The overall approach is sound, but current implementation has not yet matured enough 3.Outlook on next steps/optimizations –Implement and compare other Tree-Adders Wallace/Dadda to reduce footprint –Implement and compare a pipelined version of the Tree-Adders to reduce critical path and increase operating frequency