1. io School of Microelectronic Engineering Lecture III Single Crystal Silicon Wafer Manufacturing

2. School of Microelectronic Engineering Objectives

3. School of Microelectronic Engineering  Single crystal Si wafers the most commonly used semiconductor material in IC manufacturing.  In the original form, most solid materials exist in the form of amorphous or polycrystalline structures.  To make an industrial standard transistor, a single crystal semi- conductor substrate is required. This is due to the scattering of electron from the grain boundary can seriously affect the p-n junction characteristics. Why Single Crystal Material?

4. ` School of Microelectronic Engineering Why Silicon?  Abundant, 26% earth crust’s is silicon. One of the most abundant element on earth.  Can form a very stable and strong oxide and easy to grow.  Larger bang gap (compared to Ge), can tolerate a higher operation temperature, wider impurity range and higher breakdown voltage.

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6. ` Crystal Structure  Atomic structure of a single crystal Si unit cell  Crystal orientations are defined in Miller Indexes. MOS IC Bipolar IC

7. ` School of Microelectronic Engineering Crystal Defects  Vacancy – missing atom from crystal lattice  Interstitial defect – extra atom in between normal lattice  Frenkel defect – vacancy and interstitial in pair  Dislocation – geometric fault

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9. Dislocation

10. ` School of Microelectronic Engineering From Sand to Wafer

11. ` School of Microelectronic Engineering From Sand to Wafer  1st step: Crude Silicon or MGS (~ 99% poly-crystal silicon)

12. ` School of Microelectronic Engineering From Sand to Wafer  2nd step: High Purity TCS Formation (Trichlorosilane, SiHCl 3 )  MGS grinded into powder  MGS powder react with HCL to form TCS  TCS is purified up to 99.9999999%

13. ` School of Microelectronic Engineering From Sand to Wafer  3rd step: EGS (Electronic Grade Silicon) Formation – polycrystal form

14. School of Microelectronic Engineering From Sand to Wafer  4 th Step: Crystall Pulling  EGS to be heated at high temperature and pulled using single- Crystal silicon seed.  2 methods;  Czochralski (CZ) Method – larger diameter, lower cost, in situ doping.  Floating Zone (FZ) Method

15. School of Microelectronic Engineering From Sand to Wafer  CZ Method

16. School of Microelectronic Engineering From Sand to Wafer  CZ Method

17. School of Microelectronic Engineering From Sand to Wafer  FZ Method

18. ` School of Microelectronic Engineering FZ and CZ Comparison

19. School of Microelectronic Engineering From Sand to Wafer  5 th Step: Ingot Polishing and Wafer Sawing  Ingot polishing to remove the grooves created during pulling  Wafer slicing

20. School of Microelectronic Engineering From Sand to Wafer Typical Wafer Parameters

21. School of Microelectronic Engineering Grinding Edge Polished Slicing Lapping Polished Process Control  6 th Step: Wafer Finishing

22. School of Microelectronic Engineering Epitaxial Wafer

23. School of Microelectronic Engineering Epitaxial Wafer The most expensive process step, ~ USD 20 -100 per step compared to USD 1 per step for other process.